📄 mc9s12dg128.h
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extern volatile PARTIDHSTR _PARTIDH @(REG_BASE + 0x0000001A);
#define PARTIDH _PARTIDH.Byte
#define PARTIDH_ID15 _PARTIDH.Bits.ID15
#define PARTIDH_ID14 _PARTIDH.Bits.ID14
#define PARTIDH_ID13 _PARTIDH.Bits.ID13
#define PARTIDH_ID12 _PARTIDH.Bits.ID12
#define PARTIDH_ID11 _PARTIDH.Bits.ID11
#define PARTIDH_ID10 _PARTIDH.Bits.ID10
#define PARTIDH_ID9 _PARTIDH.Bits.ID9
#define PARTIDH_ID8 _PARTIDH.Bits.ID8
#define PARTIDH_ID15_MASK 1
#define PARTIDH_ID14_MASK 2
#define PARTIDH_ID13_MASK 4
#define PARTIDH_ID12_MASK 8
#define PARTIDH_ID11_MASK 16
#define PARTIDH_ID10_MASK 32
#define PARTIDH_ID9_MASK 64
#define PARTIDH_ID8_MASK 128
/*** PARTIDL - Part ID Register Low; 0x0000001B ***/
typedef union {
byte Byte;
struct {
byte ID0 :1; /* Part ID Register Bit 0 */
byte ID1 :1; /* Part ID Register Bit 1 */
byte ID2 :1; /* Part ID Register Bit 2 */
byte ID3 :1; /* Part ID Register Bit 3 */
byte ID4 :1; /* Part ID Register Bit 4 */
byte ID5 :1; /* Part ID Register Bit 5 */
byte ID6 :1; /* Part ID Register Bit 6 */
byte ID7 :1; /* Part ID Register Bit 7 */
} Bits;
struct {
byte grpID :8;
} MergedBits;
} PARTIDLSTR;
extern volatile PARTIDLSTR _PARTIDL @(REG_BASE + 0x0000001B);
#define PARTIDL _PARTIDL.Byte
#define PARTIDL_ID0 _PARTIDL.Bits.ID0
#define PARTIDL_ID1 _PARTIDL.Bits.ID1
#define PARTIDL_ID2 _PARTIDL.Bits.ID2
#define PARTIDL_ID3 _PARTIDL.Bits.ID3
#define PARTIDL_ID4 _PARTIDL.Bits.ID4
#define PARTIDL_ID5 _PARTIDL.Bits.ID5
#define PARTIDL_ID6 _PARTIDL.Bits.ID6
#define PARTIDL_ID7 _PARTIDL.Bits.ID7
#define PARTIDL_ID _PARTIDL.MergedBits.grpID
#define PARTIDL_ID0_MASK 1
#define PARTIDL_ID1_MASK 2
#define PARTIDL_ID2_MASK 4
#define PARTIDL_ID3_MASK 8
#define PARTIDL_ID4_MASK 16
#define PARTIDL_ID5_MASK 32
#define PARTIDL_ID6_MASK 64
#define PARTIDL_ID7_MASK 128
#define PARTIDL_ID_MASK 255
#define PARTIDL_ID_BITNUM 0
/*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***/
typedef union {
byte Byte;
struct {
byte ram_sw0 :1; /* Allocated RAM Memory Space Bit 0 */
byte ram_sw1 :1; /* Allocated RAM Memory Space Bit 1 */
byte ram_sw2 :1; /* Allocated RAM Memory Space Bit 2 */
byte :1;
byte eep_sw0 :1; /* Allocated EEPROM Memory Space Bit 0 */
byte eep_sw1 :1; /* Allocated EEPROM Memory Space Bit 1 */
byte :1;
byte reg_sw0 :1; /* Allocated System Register Space */
} Bits;
struct {
byte grpram_sw :3;
byte :1;
byte grpeep_sw :2;
byte :1;
byte grpreg_sw :1;
} MergedBits;
} MEMSIZ0STR;
extern volatile MEMSIZ0STR _MEMSIZ0 @(REG_BASE + 0x0000001C);
#define MEMSIZ0 _MEMSIZ0.Byte
#define MEMSIZ0_ram_sw0 _MEMSIZ0.Bits.ram_sw0
#define MEMSIZ0_ram_sw1 _MEMSIZ0.Bits.ram_sw1
#define MEMSIZ0_ram_sw2 _MEMSIZ0.Bits.ram_sw2
#define MEMSIZ0_eep_sw0 _MEMSIZ0.Bits.eep_sw0
#define MEMSIZ0_eep_sw1 _MEMSIZ0.Bits.eep_sw1
#define MEMSIZ0_reg_sw0 _MEMSIZ0.Bits.reg_sw0
#define MEMSIZ0_ram_sw _MEMSIZ0.MergedBits.grpram_sw
#define MEMSIZ0_eep_sw _MEMSIZ0.MergedBits.grpeep_sw
#define MEMSIZ0_ram_sw0_MASK 1
#define MEMSIZ0_ram_sw1_MASK 2
#define MEMSIZ0_ram_sw2_MASK 4
#define MEMSIZ0_eep_sw0_MASK 16
#define MEMSIZ0_eep_sw1_MASK 32
#define MEMSIZ0_reg_sw0_MASK 128
#define MEMSIZ0_ram_sw_MASK 7
#define MEMSIZ0_ram_sw_BITNUM 0
#define MEMSIZ0_eep_sw_MASK 48
#define MEMSIZ0_eep_sw_BITNUM 4
/*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***/
typedef union {
byte Byte;
struct {
byte pag_sw0 :1; /* Allocated Off-Chip Memory Options Bit 0 */
byte pag_sw1 :1; /* Allocated Off-Chip Memory Options Bit 1 */
byte :1;
byte :1;
byte :1;
byte :1;
byte rom_sw0 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 0 */
byte rom_sw1 :1; /* Allocated Flash EEPROM/ROM Physical Memory Space Bit 1 */
} Bits;
struct {
byte grppag_sw :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte grprom_sw :2;
} MergedBits;
} MEMSIZ1STR;
extern volatile MEMSIZ1STR _MEMSIZ1 @(REG_BASE + 0x0000001D);
#define MEMSIZ1 _MEMSIZ1.Byte
#define MEMSIZ1_pag_sw0 _MEMSIZ1.Bits.pag_sw0
#define MEMSIZ1_pag_sw1 _MEMSIZ1.Bits.pag_sw1
#define MEMSIZ1_rom_sw0 _MEMSIZ1.Bits.rom_sw0
#define MEMSIZ1_rom_sw1 _MEMSIZ1.Bits.rom_sw1
#define MEMSIZ1_pag_sw _MEMSIZ1.MergedBits.grppag_sw
#define MEMSIZ1_rom_sw _MEMSIZ1.MergedBits.grprom_sw
#define MEMSIZ1_pag_sw0_MASK 1
#define MEMSIZ1_pag_sw1_MASK 2
#define MEMSIZ1_rom_sw0_MASK 64
#define MEMSIZ1_rom_sw1_MASK 128
#define MEMSIZ1_pag_sw_MASK 3
#define MEMSIZ1_pag_sw_BITNUM 0
#define MEMSIZ1_rom_sw_MASK 192
#define MEMSIZ1_rom_sw_BITNUM 6
/*** INTCR - Interrupt Control Register; 0x0000001E ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte IRQEN :1; /* External IRQ Enable */
byte IRQE :1; /* IRQ Select Edge Sensitive Only */
} Bits;
} INTCRSTR;
extern volatile INTCRSTR _INTCR @(REG_BASE + 0x0000001E);
#define INTCR _INTCR.Byte
#define INTCR_IRQEN _INTCR.Bits.IRQEN
#define INTCR_IRQE _INTCR.Bits.IRQE
#define INTCR_IRQEN_MASK 64
#define INTCR_IRQE_MASK 128
/*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***/
typedef union {
byte Byte;
struct {
byte :1;
byte PSEL1 :1; /* Highest Priority I Interrupt Bit 1 */
byte PSEL2 :1; /* Highest Priority I Interrupt Bit 2 */
byte PSEL3 :1; /* Highest Priority I Interrupt Bit 3 */
byte PSEL4 :1; /* Highest Priority I Interrupt Bit 4 */
byte PSEL5 :1; /* Highest Priority I Interrupt Bit 5 */
byte PSEL6 :1; /* Highest Priority I Interrupt Bit 6 */
byte PSEL7 :1; /* Highest Priority I Interrupt Bit 7 */
} Bits;
struct {
byte :1;
byte grpPSEL_1 :7;
} MergedBits;
} HPRIOSTR;
extern volatile HPRIOSTR _HPRIO @(REG_BASE + 0x0000001F);
#define HPRIO _HPRIO.Byte
#define HPRIO_PSEL1 _HPRIO.Bits.PSEL1
#define HPRIO_PSEL2 _HPRIO.Bits.PSEL2
#define HPRIO_PSEL3 _HPRIO.Bits.PSEL3
#define HPRIO_PSEL4 _HPRIO.Bits.PSEL4
#define HPRIO_PSEL5 _HPRIO.Bits.PSEL5
#define HPRIO_PSEL6 _HPRIO.Bits.PSEL6
#define HPRIO_PSEL7 _HPRIO.Bits.PSEL7
#define HPRIO_PSEL_1 _HPRIO.MergedBits.grpPSEL_1
#define HPRIO_PSEL HPRIO_PSEL_1
#define HPRIO_PSEL1_MASK 2
#define HPRIO_PSEL2_MASK 4
#define HPRIO_PSEL3_MASK 8
#define HPRIO_PSEL4_MASK 16
#define HPRIO_PSEL5_MASK 32
#define HPRIO_PSEL6_MASK 64
#define HPRIO_PSEL7_MASK 128
#define HPRIO_PSEL_1_MASK 254
#define HPRIO_PSEL_1_BITNUM 1
/*** BKPCT0 - Breakpoint Control Register 0; 0x00000028 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte BKTAG :1; /* Breakpoint on Tag */
byte BKBDM :1; /* Breakpoint Background Debug Mode Enable */
byte BKFULL :1; /* Full Breakpoint Mode Enable */
byte BKEN :1; /* Breakpoint Enable */
} Bits;
} BKPCT0STR;
extern volatile BKPCT0STR _BKPCT0 @(REG_BASE + 0x00000028);
#define BKPCT0 _BKPCT0.Byte
#define BKPCT0_BKTAG _BKPCT0.Bits.BKTAG
#define BKPCT0_BKBDM _BKPCT0.Bits.BKBDM
#define BKPCT0_BKFULL _BKPCT0.Bits.BKFULL
#define BKPCT0_BKEN _BKPCT0.Bits.BKEN
#define BKPCT0_BKTAG_MASK 16
#define BKPCT0_BKBDM_MASK 32
#define BKPCT0_BKFULL_MASK 64
#define BKPCT0_BKEN_MASK 128
/*** BKPCT1 - Breakpoint Control Register 1; 0x00000029 ***/
typedef union {
byte Byte;
struct {
byte BK1RW :1; /* R/W Compare Value 1 */
byte BK1RWE :1; /* R/W Compare Enable 1 */
byte BK0RW :1; /* R/W Compare Value 0 */
byte BK0RWE :1; /* R/W Compare Enable 0 */
byte BK1MBL :1; /* Breakpoint Mask Low Byte for Second Address */
byte BK1MBH :1; /* Breakpoint Mask High Byte for Second Address */
byte BK0MBL :1; /* Breakpoint Mask Low Byte for First Address */
byte BK0MBH :1; /* Breakpoint Mask High Byte for First Address */
} Bits;
} BKPCT1STR;
extern volatile BKPCT1STR _BKPCT1 @(REG_BASE + 0x00000029);
#define BKPCT1 _BKPCT1.Byte
#define BKPCT1_BK1RW _BKPCT1.Bits.BK1RW
#define BKPCT1_BK1RWE _BKPCT1.Bits.BK1RWE
#define BKPCT1_BK0RW _BKPCT1.Bits.BK0RW
#define BKPCT1_BK0RWE _BKPCT1.Bits.BK0RWE
#define BKPCT1_BK1MBL _BKPCT1.Bits.BK1MBL
#define BKPCT1_BK1MBH _BKPCT1.Bits.BK1MBH
#define BKPCT1_BK0MBL _BKPCT1.Bits.BK0MBL
#define BKPCT1_BK0MBH _BKPCT1.Bits.BK0MBH
#define BKPCT1_BK1RW_MASK 1
#define BKPCT1_BK1RWE_MASK 2
#define BKPCT1_BK0RW_MASK 4
#define BKPCT1_BK0RWE_MASK 8
#define BKPCT1_BK1MBL_MASK 16
#define BKPCT1_BK1MBH_MASK 32
#define BKPCT1_BK0MBL_MASK 64
#define BKPCT1_BK0MBH_MASK 128
/*** BKP0X - First Address Memory Expansion Breakpoint Register; 0x0000002A ***/
typedef union {
byte Byte;
struct {
byte BK0V0 :1; /* First Address Breakpoint Expansion Address Value Bit 0 */
byte BK0V1 :1; /* First Address Breakpoint Expansion Address Value Bit 1 */
byte BK0V2 :1; /* First Address Breakpoint Expansion Address Value Bit 2 */
byte BK0V3 :1; /* First Address Breakpoint Expansion Address Value Bit 3 */
byte BK0V4 :1; /* First Address Breakpoint Expansion Address Value Bit 4 */
byte BK0V5 :1; /* First Address Breakpoint Expansion Address Value Bit 5 */
byte :1;
byte :1;
} Bits;
struct {
byte grpBK0V :6;
byte :1;
byte :1;
} MergedBits;
} BKP0XSTR;
extern volatile BKP0XSTR _BKP0X @(REG_BASE + 0x0000002A);
#define BKP0X _BKP0X.Byte
#define BKP0X_BK0V0 _BKP0X.Bits.BK0V0
#define BKP0X_BK0V1 _BKP0X.Bits.BK0V1
#define BKP0X_BK0V2 _BKP0X.Bits.BK0V2
#define BKP0X_BK0V3 _BKP0X.Bits.BK0V3
#define BKP0X_BK0V4 _BKP0X.Bits.BK0V4
#define BKP0X_BK0V5 _BKP0X.Bits.BK0V5
#define BKP0X_BK0V _BKP0X.MergedBits.grpBK0V
#define BKP0X_BK0V0_MASK 1
#define BKP0X_BK0V1_MASK 2
#define BKP0X_BK0V2_MASK 4
#define BKP0X_BK0V3_MASK 8
#define BKP0X_BK0V4_MASK 16
#define BKP0X_BK0V5_MASK 32
#define BKP0X_BK0V_MASK 63
#define BKP0X_BK0V_BITNUM 0
/*** BKP0H - First Address High Byte Breakpoint Register; 0x0000002B ***/
typedef union {
byte Byte;
struct {
byte BIT8 :1; /* First Address Breakpoint Register Bit 8 */
byte BIT9 :1; /* First Address Breakpoint Register Bit 9 */
byte BIT10 :1; /* First Address Breakpoint Register Bit 10 */
byte BIT11 :1; /* First Address Breakpoint Register Bit 11 */
byte BIT12 :1; /* First Address Breakpoint Register Bit 12 */
byte BIT13 :1; /* First Address Breakpoint Register Bit 13 */
byte BIT14 :1; /* First Address Breakpoint Register Bit 14 */
byte BIT15 :1; /* First Address Breakpoint Register Bit 15 */
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