📄 atmegal16l.lst
字号:
(0087) **修改说明:
(0088) **************************************/
(0089) void timer1_init(void)
(0090) {
(0091) TCCR1B = 0x00; //stop
_timer1_init:
03D1 2422 CLR R2
03D2 BC2E OUT 0x2E,R2
(0092) TCNT1H = 0x00; //setup
03D3 BC2D OUT 0x2D,R2
(0093) TCNT1L = 0x00;
03D4 BC2C OUT 0x2C,R2
(0094) OCR1AH = 0xFF;
03D5 EF8F LDI R24,0xFF
03D6 BD8B OUT 0x2B,R24
(0095) OCR1AL = 0xFF;
03D7 BD8A OUT 0x2A,R24
(0096) OCR1BH = 0xFF;
03D8 BD89 OUT 0x29,R24
(0097) OCR1BL = 0xFF;
03D9 BD88 OUT 0x28,R24
(0098) TCCR1A = 0x00;
03DA BC2F OUT 0x2F,R2
(0099) }
03DB 9508 RET
(0100) /**************************************
(0101) **芯片类型:ATmega16
(0102) **时钟频率:8M
(0103) **硬件接口说明:无
(0104) **函数功能说明:对外部中断0进行初始化,设置为下降沿触发
(0105) **函数输入参数及说明:无
(0106) **函数返回值:无
(0107) **在本函数以外定义的变量:无
(0108) **调用的函数说明:无
(0109) **修改人:
(0110) **修改日期:
(0111) **修改说明:
(0112) **************************************/
(0113)
(0114) void ext_init(void)
(0115) {
(0116) MCUCR=0x02;
_ext_init:
03DC E082 LDI R24,2
03DD BF85 OUT 0x35,R24
(0117) GICR=0x40; //设置外中断0为下降沿触发
03DE E480 LDI R24,0x40
03DF BF8B OUT 0x3B,R24
(0118) }
03E0 9508 RET
(0119)
(0120) /**************************************
(0121) **芯片类型:ATmega16
(0122) **时钟频率:8M
(0123) **硬件接口说明:无
(0124) **函数功能说明:对端口、串口、定时器0、1进行初始化
(0125) **函数输入参数及说明:无
(0126) **函数返回值:无
(0127) **在本函数以外定义的变量:无
(0128) **调用的函数说明:port_init()、uart0_init()、timer0_init()、timer1_init()
(0129) **修改人:
(0130) **修改日期:
(0131) **修改说明:
(0132) **************************************/
(0133) void init_devices(void)
(0134) {
(0135) CLI(); //关中断
_init_devices:
03E1 94F8 BCLR 7
(0136) port_init();
03E2 DFD0 RCALL _port_init
(0137) uart0_init();
03E3 DFDB RCALL _uart0_init
(0138) timer0_init();
03E4 DFE5 RCALL _timer0_init
(0139) timer1_init();
03E5 DFEB RCALL _timer1_init
(0140) MCUCR = 0x00;
03E6 2422 CLR R2
03E7 BE25 OUT 0x35,R2
(0141) GICR = 0x00;
03E8 BE2B OUT 0x3B,R2
(0142) TIMSK = 0x05; //T/C0、1中断中断使能
03E9 E085 LDI R24,5
03EA BF89 OUT 0x39,R24
(0143)
(0144) SEI(); //开中断
03EB 9478 BSET 7
(0145) }
03EC 9508 RET
(0146) //============================================================
(0147) //看门狗初始化函数
(0148) //
(0149) //
(0150) //
(0151) //
(0152) //============================================================
(0153) void watchdog_init(void)
(0154) {
(0155) WDR(); //this prevents a timout on enabling
_watchdog_init:
03ED 95A8 WDR
(0156) WDTCR = 0x08; //WATCHDOG ENABLED - dont forget to issue WDRs
03EE E088 LDI R24,0x8
03EF BD81 OUT 0x21,R24
(0157) }
FILE: <library>
03F0 9508 RET
push_arg4:
03F1 933A ST R19,-Y
03F2 932A ST R18,-Y
push_arg2:
03F3 931A ST R17,-Y
03F4 930A ST R16,-Y
03F5 9508 RET
empy16s:
03F6 920A ST R0,-Y
03F7 921A ST R1,-Y
03F8 938A ST R24,-Y
03F9 939A ST R25,-Y
03FA 9F02 MUL R16,R18
03FB 01C0 MOVW R24,R0
03FC 9F12 MUL R17,R18
03FD 0D90 ADD R25,R0
03FE 9F03 MUL R16,R19
03FF 0D90 ADD R25,R0
0400 018C MOVW R16,R24
0401 9199 LD R25,Y+
0402 9189 LD R24,Y+
0403 9019 LD R1,Y+
0404 9009 LD R0,Y+
0405 9508 RET
pop_gset2:
0406 E0E2 LDI R30,2
0407 940C0416 JMP pop
pop_gset3:
0409 E0E4 LDI R30,4
040A 940C0416 JMP pop
pop_gset4:
040C E0E8 LDI R30,0x8
040D 940C0416 JMP pop
pop_gset5:
040F 27EE CLR R30
0410 940C0416 JMP pop
push_gset1:
0412 935A ST R21,-Y
0413 934A ST R20,-Y
0414 9508 RET
pop_gset1:
0415 E0E1 LDI R30,1
pop:
0416 9149 LD R20,Y+
0417 9159 LD R21,Y+
0418 FDE0 SBRC R30,0
0419 9508 RET
041A 9169 LD R22,Y+
041B 9179 LD R23,Y+
041C FDE1 SBRC R30,1
041D 9508 RET
041E 90A9 LD R10,Y+
041F 90B9 LD R11,Y+
0420 FDE2 SBRC R30,2
0421 9508 RET
0422 90C9 LD R12,Y+
0423 90D9 LD R13,Y+
0424 FDE3 SBRC R30,3
0425 9508 RET
0426 90E9 LD R14,Y+
0427 90F9 LD R15,Y+
0428 9508 RET
push_gset2:
0429 937A ST R23,-Y
042A 936A ST R22,-Y
042B 940C0412 JMP push_gset1
push_gset3:
042D 92BA ST R11,-Y
042E 92AA ST R10,-Y
042F 940C0429 JMP push_gset2
push_gset4:
0431 92DA ST R13,-Y
0432 92CA ST R12,-Y
0433 940C042D JMP push_gset3
push_gset5:
0435 92FA ST R15,-Y
0436 92EA ST R14,-Y
0437 940C0431 JMP push_gset4
neg32:
0439 9500 COM R16
043A 9510 COM R17
043B 9520 COM R18
043C 9530 COM R19
043D 5F0F SUBI R16,0xFF
043E 4F1F SBCI R17,0xFF
043F 4F2F SBCI R18,0xFF
0440 4F3F SBCI R19,0xFF
0441 9508 RET
lpm32:
0442 93EA ST R30,-Y
0443 93FA ST R31,-Y
0444 920A ST R0,-Y
0445 2FE0 MOV R30,R16
0446 2FF1 MOV R31,R17
0447 95C8 LPM
0448 2D00 MOV R16,R0
0449 9631 ADIW R30,1
044A 95C8 LPM
044B 2D10 MOV R17,R0
044C 9631 ADIW R30,1
044D 95C8 LPM
044E 2D20 MOV R18,R0
044F 9631 ADIW R30,1
0450 95C8 LPM
0451 2D30 MOV R19,R0
0452 9009 LD R0,Y+
0453 91F9 LD R31,Y+
0454 91E9 LD R30,Y+
0455 9508 RET
int2fp:
0456 2722 CLR R18
0457 FD17 SBRC R17,7
0458 9520 COM R18
0459 2733 CLR R19
045A FD27 SBRC R18,7
045B 9530 COM R19
long2fp:
045C 940E0568 CALL savfacc1
045E D002 RCALL ITOF
045F 940C056B JMP restorefacc1
ITOF:
0461 2788 CLR R24
0462 2333 TST R19
0463 F41A BPL 0x0467
0464 940E0439 CALL neg32
0466 9580 COM R24
0467 2FB0 MOV R27,R16
0468 2BB1 OR R27,R17
0469 2BB2 OR R27,R18
046A 2BB3 OR R27,R19
046B F411 BNE 0x046E
046C 940C0584 JMP minres
046E E1B6 LDI R27,0x16
046F C005 RJMP 0x0475
0470 95B3 INC R27
0471 9536 LSR R19
0472 9527 ROR R18
0473 9517 ROR R17
0474 9507 ROR R16
0475 2333 TST R19
0476 F7C9 BNE 0x0470
0477 2322 TST R18
0478 F449 BNE 0x0482
0479 50B8 SUBI R27,0x8
047A 2F21 MOV R18,R17
047B 2F10 MOV R17,R16
047C E000 LDI R16,0
047D CFF9 RJMP 0x0477
047E 95BA DEC R27
047F 0F00 LSL R16
0480 1F11 ROL R17
0481 1F22 ROL R18
0482 F7DA BPL 0x047E
0483 2F3B MOV R19,R27
0484 940C05AE JMP repack
save_floatregs:
0486 92DA ST R13,-Y
0487 92EA ST R14,-Y
0488 92FA ST R15,-Y
0489 938A ST R24,-Y
048A 922A ST R2,-Y
048B 923A ST R3,-Y
048C 924A ST R4,-Y
048D 939A ST R25,-Y
048E 93AA ST R26,-Y
048F 93BA ST R27,-Y
0490 9508 RET
restore_floatregs:
0491 91B9 LD R27,Y+
0492 91A9 LD R26,Y+
0493 9199 LD R25,Y+
0494 9049 LD R4,Y+
0495 9039 LD R3,Y+
0496 9029 LD R2,Y+
0497 9189 LD R24,Y+
0498 90F9 LD R15,Y+
0499 90E9 LD R14,Y+
049A 90D9 LD R13,Y+
049B 9508 RET
stk2arg1:
049C 842A LDD R2,Y+10
049D 843B LDD R3,Y+11
049E 844C LDD R4,Y+12
049F 859D LDD R25,Y+13
04A0 9508 RET
stk2arg0:
04A1 850E LDD R16,Y+14
04A2 851F LDD R17,Y+15
04A3 8928 LDD R18,Y+16
04A4 8939 LDD R19,Y+17
04A5 9508 RET
float_epilog:
04A6 DFEA RCALL restore_floatregs
04A7 920F PUSH R0
04A8 B60F IN R0,0x3F
04A9 9628 ADIW R28,0x8
04AA BE0F OUT 0x3F,R0
04AB 900F POP R0
04AC 9508 RET
float_prolog:
04AD DFD8 RCALL save_floatregs
04AE DFF2 RCALL stk2arg0
04AF CFEC RJMP stk2arg1
add32fs:
04B0 D002 RCALL add32f
04B1 940C03F1 JMP push_arg4
add32f:
04B3 940E04AD CALL float_prolog
04B5 D012 RCALL FADD
04B6 940C04A6 JMP float_epilog
sub32fs:
04B8 D002 RCALL sub32f
04B9 940C03F1 JMP push_arg4
sub32f:
04BB 940E04AD CALL float_prolog
04BD D009 RCALL FSUB
04BE 940C04A6 JMP float_epilog
fret2:
04C0 2F8A MOV R24,R26
04C1 2F39 MOV R19,R25
04C2 2D24 MOV R18,R4
04C3 2D13 MOV R17,R3
04C4 2D02 MOV R16,R2
04C5 940C05AE JMP repack
FSUB:
04C7 5890 SUBI R25,0x80
FADD:
04C8 940E059C CALL unpack
04CA 3890 CPI R25,0x80
04CB F3C9 BEQ 0x04C5
04CC 3830 CPI R19,0x80
04CD F391 BEQ 0x04C0
04CE 2FB3 MOV R27,R19
04CF 1BB9 SUB R27,R25
04D0 F3A3 BVS 0x04C5
04D1 F02A BMI 0x04D7
04D2 F439 BNE 0x04DA
04D3 1502 CP R16,R2
04D4 0513 CPC R17,R3
04D5 0524 CPC R18,R4
04D6 F418 BCC 0x04DA
04D7 940E0590 CALL swapacc
04D9 CFF4 RJMP 0x04CE
04DA 31B8 CPI R27,0x18
04DB F018 BCS 0x04DF
04DC 2422 CLR R2
04DD 2433 CLR R3
04DE 2444 CLR R4
04DF 30B8 CPI R27,0x8
04E0 F028 BCS 0x04E6
04E1 2C23 MOV R2,R3
04E2 2C34 MOV R3,R4
04E3 2444 CLR R4
04E4 50B8 SUBI R27,0x8
04E5 CFF9 RJMP 0x04DF
04E6 23BB TST R27
04E7 F029 BEQ 0x04ED
04E8 9446 LSR R4
04E9 9437 ROR R3
04EA 9427 ROR R2
04EB 95BA DEC R27
04EC F7D9 BNE 0x04E8
04ED 2FB8 MOV R27,R24
04EE 27BA EOR R27,R26
04EF F04A BMI 0x04F9
04F0 D018 RCALL 0x0509
04F1 F698 BCC 0x04C5
04F2 9527 ROR R18
04F3 9517 ROR R17
04F4 9507 ROR R16
04F5 5F3F SUBI R19,0xFF
04F6 F673 BVC 0x04C5
04F7 940C057D JMP maxres
04F9 D013 RCALL usub24
04FA F411 BNE 0x04FD
04FB 940C0584 JMP minres
04FD F410 BCC 0x0500
04FE 940E0577 CALL negmant
0500 2322 TST R18
0501 F21A BMI 0x04C5
0502 0F00 LSL R16
0503 1F11 ROL R17
0504 1F22 ROL R18
0505 5031 SUBI R19,1
0506 F7CB BVC 0x0500
0507 940C057D JMP maxres
0509 0D02 ADD R16,R2
050A 1D13 ADC R17,R3
050B 1D24 ADC R18,R4
050C 9508 RET
usub24:
050D 1902 SUB R16,R2
050E 0913 SBC R17,R3
050F 0924 SBC R18,R4
0510 9508 RET
0511 E7BF LDI R27,0x7F
0512 2F3B MOV R19,R27
0513 2B2B OR R18,R27
0514 EF0F LDI R16,0xFF
0515 EF1F LDI R17,0xFF
0516 9508 RET
0517 2700 CLR R16
0518 2711 CLR R17
0519 2722
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