xbus_slave_seq_lib.sv

Open Verification Methodology

// $Id: //dvt/vtech/dev/main/ovm/examples/xbus/sv/xbus_slave_seq_lib.sv#4 $
//----------------------------------------------------------------------
//   Copyright 2007-2008 Mentor Graphics Corporation
//   Copyright 2007-2008 Cadence Design Systems, Inc.
//   All Rights Reserved Worldwide
//
//   Licensed under the Apache License, Version 2.0 (the
//   "License"); you may not use this file except in
//   compliance with the License.  You may obtain a copy of
//   the License at
//
//       http://www.apache.org/licenses/LICENSE-2.0
//
//   Unless required by applicable law or agreed to in
//   writing, software distributed under the License is
//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//   CONDITIONS OF ANY KIND, either express or implied.  See
//   the License for the specific language governing
//   permissions and limitations under the License.
//----------------------------------------------------------------------

`ifndef XBUS_SLAVE_SEQ_LIB_SV
`define XBUS_SLAVE_SEQ_LIB_SV

//------------------------------------------------------------------------------
//
// SEQUENCE: simple_response_seq
//
//------------------------------------------------------------------------------

class simple_response_seq extends ovm_sequence;

    function new(string name="simple_response_seq");
      super.new(name);
    endfunction

    `ovm_sequence_utils(simple_response_seq, xbus_slave_sequencer)

    xbus_transfer this_transfer;
    xbus_transfer util_transfer;

    virtual task body();
      `message(OVM_MEDIUM,("Starting sequence"))
      forever begin
        p_sequencer.addr_ph_port.get(util_transfer);
        `ovm_do_with(this_transfer, 
          { read_write == util_transfer.read_write; 
            size == util_transfer.size; 
            error_pos == 1000; } )
      end
    endtask : body

endclass : simple_response_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: slave_memory_seq
//
//------------------------------------------------------------------------------

class slave_memory_seq extends ovm_sequence;

  function new(string name="slave_memory_seq");
    super.new(name);
  endfunction

  `ovm_sequence_utils(slave_memory_seq, xbus_slave_sequencer)

  xbus_transfer this_transfer;
  xbus_transfer util_transfer;

  int unsigned m_mem[int unsigned];
  bit [7:0] temp_data[];

  virtual task body();
    `message(OVM_MEDIUM,("Starting sequence")) 
    forever
    begin
      p_sequencer.addr_ph_port.peek(util_transfer);
      //READ, i.e.  util_transfer.read_write == READ
      if( util_transfer.read_write == READ ) begin : READ_block
        temp_data = new[util_transfer.size];
        for(int unsigned i = 0 ; i < util_transfer.size ; i ++) begin
          if (!m_mem.exists(util_transfer.addr + i)) begin
            m_mem[util_transfer.addr + i] = $urandom;
          end
          temp_data[i] = m_mem[util_transfer.addr + i];
        end
        `ovm_do_with(this_transfer, 
          { addr == util_transfer.addr;
            read_write == util_transfer.read_write;
            size == util_transfer.size;
            foreach (data[i]) data[i] == temp_data[i];
            foreach (wait_state[i]) wait_state[i] == 2;
            error_pos == 1000;
            transmit_delay == 0; } )
      end : READ_block
      //WRITE, i.e.  util_transfer.read_write == WRITE
      if( util_transfer.read_write == WRITE ) begin : WRITE_block
        `ovm_do_with(this_transfer, 
          { addr == util_transfer.addr;
            read_write == util_transfer.read_write;
            size == util_transfer.size;
            foreach (wait_state[i]) wait_state[i] == 0; } )
        for(int unsigned i = 0 ; i < this_transfer.size ; i ++) begin : for_block
          m_mem[this_transfer.addr + i] = this_transfer.data[i] ;
        end : for_block
      end : WRITE_block
    end
  endtask : body

endclass : slave_memory_seq

`endif // XBUS_SLAVE_SEQ_LIB_SV