xbus_master_seq_lib.sv

Open Verification Methodology

// $Id: //dvt/vtech/dev/main/ovm/examples/xbus/sv/xbus_master_seq_lib.sv#4 $
//----------------------------------------------------------------------
//   Copyright 2007-2008 Mentor Graphics Corporation
//   Copyright 2007-2008 Cadence Design Systems, Inc.
//   All Rights Reserved Worldwide
//
//   Licensed under the Apache License, Version 2.0 (the
//   "License"); you may not use this file except in
//   compliance with the License.  You may obtain a copy of
//   the License at
//
//       http://www.apache.org/licenses/LICENSE-2.0
//
//   Unless required by applicable law or agreed to in
//   writing, software distributed under the License is
//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//   CONDITIONS OF ANY KIND, either express or implied.  See
//   the License for the specific language governing
//   permissions and limitations under the License.
//----------------------------------------------------------------------

`ifndef XBUS_MASTER_SEQ_LIB_SV
`define XBUS_MASTER_SEQ_LIB_SV

//------------------------------------------------------------------------------
//
// SEQUENCE: read_byte
//
//------------------------------------------------------------------------------

class read_byte_seq extends ovm_sequence;

  function new(string name="read_byte_seq");
    super.new(name);
  endfunction
  
  `ovm_sequence_utils(read_byte_seq, xbus_master_sequencer)    

  xbus_transfer this_transfer;

  rand bit [15:0] start_addr;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { (transmit_del <= 10); }

  virtual task body();
    `ovm_do_with(this_transfer, 
      { addr == start_addr;
        read_write == READ;
        size == 1;
        error_pos == 1000;
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Reading : addr = `x%0h, data[0] = `x%0h",
      this_transfer.addr, this_transfer.data[0]))
  endtask
  
endclass : read_byte_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: read_half_word_seq
//
//------------------------------------------------------------------------------

class read_half_word_seq extends ovm_sequence;

  function new(string name="read_half_word_seq");
    super.new(name);
  endfunction
  
  `ovm_sequence_utils(read_half_word_seq, xbus_master_sequencer)

  xbus_transfer this_transfer;

  rand bit [15:0] start_addr;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { (transmit_del <= 10); }

  virtual task body();
    `ovm_do_with(this_transfer, 
      { addr == start_addr;
        read_write == READ;
        size == 2;
        error_pos == 1000;
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Reading : addr = `x%0h, data[0] = `x%0h, \
      data[1] = `x%0h", this_transfer.addr, this_transfer.data[0],
      this_transfer.data[1]))
  endtask

endclass : read_half_word_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: read_word_seq
//
//------------------------------------------------------------------------------

class read_word_seq extends ovm_sequence;

  function new(string name="read_word_seq");
    super.new(name);
  endfunction
  
  `ovm_sequence_utils(read_word_seq, xbus_master_sequencer)

  xbus_transfer this_transfer;

  rand bit [15:0] start_addr;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { (transmit_del <= 10); }

  virtual task body();
    `ovm_do_with(this_transfer, 
      { addr == start_addr;
        read_write == READ;
        size == 4;
        error_pos == 1000;
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Reading : addr = `x%0h, data[0] = `x%0h, \
      data[1] = `x%0h, data[2] = `x%0h, data[3] = `x%0h",
      this_transfer.addr, this_transfer.data[0],
      this_transfer.data[1], this_transfer.data[2],
      this_transfer.data[3]))
  endtask
  
endclass : read_word_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: read_double_word_seq
//
//------------------------------------------------------------------------------

class read_double_word_seq extends ovm_sequence;

  function new(string name="read_double_word_seq");
    super.new(name);
  endfunction
  
  `ovm_sequence_utils(read_double_word_seq, xbus_master_sequencer)    

  xbus_transfer this_transfer;
  
  rand bit [15:0] start_addr;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { (transmit_del <= 10); }

  virtual task body();
    `ovm_do_with(this_transfer, 
      { addr == start_addr;
        read_write == READ;
        size == 8;
        error_pos == 1000;
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Reading : addr = `x%0h, data[0] = `x%0h, \
      data[1] = `x%0h, data[2] = `x%0h, data[3] = `x%0h, data[4] = `x%0h, \
      data[5] = `x%0h, data[6] = `x%0h, data[7] = `x%0h",
      this_transfer.addr, this_transfer.data[0],
      this_transfer.data[1], this_transfer.data[2],
      this_transfer.data[3], this_transfer.data[4],
      this_transfer.data[5], this_transfer.data[6],
      this_transfer.data[7]))
  endtask
  
endclass : read_double_word_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: write_byte_seq
//
//------------------------------------------------------------------------------

class write_byte_seq extends ovm_sequence;

  function new(string name="write_byte_seq");
    super.new(name);
  endfunction

  `ovm_sequence_utils(write_byte_seq, xbus_master_sequencer)
    
  xbus_transfer this_transfer;

  rand bit [15:0] start_addr;
  rand bit [7:0]  data0;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { (transmit_del <= 10); }

  virtual task body();
    `ovm_do_with(this_transfer, 
      { addr == start_addr;
        read_write == WRITE;
        size == 1;
        data[0] == data0;
        error_pos == 1000;
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Writing : addr = `x%0h, data[0] = `x%0h",
      this_transfer.addr, this_transfer.data[0]))
  endtask

endclass : write_byte_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: write_half_word_seq
//
//------------------------------------------------------------------------------

class write_half_word_seq extends ovm_sequence;

  function new(string name="write_half_word_seq");
    super.new(name);
  endfunction

  `ovm_sequence_utils(write_half_word_seq, xbus_master_sequencer)
    
  xbus_transfer this_transfer;
  bit [7:0] temp_data[];

  rand bit [15:0] start_addr;
  rand bit [7:0]  data0;
  rand bit [7:0]  data1;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { transmit_del <= 10; }

  virtual task body();
    temp_data = new[2]; 
    temp_data[0] = data0; temp_data[1] = data1;
    `ovm_do_with(this_transfer, 
      { addr == start_addr; 
        read_write == WRITE;
        size == 2; 
        foreach (data[i]) data[i] == temp_data[i];
        error_pos == 1000; 
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Writing : addr = `x%0h, data[0] = `x%0h, \
      data[1] = `x%0h", this_transfer.addr, this_transfer.data[0],
      this_transfer.data[1]))
  endtask

endclass : write_half_word_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: write_word_seq
//
//------------------------------------------------------------------------------

class write_word_seq extends ovm_sequence;

  function new(string name="write_word_seq");
    super.new(name);
  endfunction

  `ovm_sequence_utils(write_word_seq, xbus_master_sequencer)
    
  xbus_transfer this_transfer;
  bit [7:0] temp_data[];

  rand bit [15:0] start_addr;
  rand bit [7:0]  data0; rand bit [7:0]  data1;
  rand bit [7:0]  data2; rand bit [7:0]  data3;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { (transmit_del <= 10); }

  virtual task body();
    temp_data = new[4];
    temp_data[0] = data0; temp_data[1] = data1;
    temp_data[2] = data2; temp_data[3] = data3;
    `ovm_do_with(this_transfer, 
      { addr == start_addr;
        read_write == WRITE;
        size == 4;
        foreach (data[i]) data[i] == temp_data[i];
        error_pos == 1000;
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Writing : addr = `x%0h, data[0] = `x%0h, \
      data[1] = `x%0h, data[2] = `x%0h, data[3] = `x%0h",
      this_transfer.addr, this_transfer.data[0],
      this_transfer.data[1], this_transfer.data[2],
      this_transfer.data[3]))
  endtask

endclass : write_word_seq


//------------------------------------------------------------------------------
//
// SEQUENCE: write_double_word_seq
//
//------------------------------------------------------------------------------

class write_double_word_seq extends ovm_sequence;

  function new(string name="write_double_word_seq");
    super.new(name);
  endfunction

  `ovm_sequence_utils(write_double_word_seq, xbus_master_sequencer)
    
  xbus_transfer this_transfer;
  bit [7:0] temp_data[];

  rand bit [15:0] start_addr;
  rand bit [7:0]  data0; rand bit [7:0]  data1;
  rand bit [7:0]  data2; rand bit [7:0]  data3;
  rand bit [7:0]  data4; rand bit [7:0]  data5;
  rand bit [7:0]  data6; rand bit [7:0]  data7;
  rand int unsigned transmit_del = 0;
  constraint transmit_del_ct { (transmit_del <= 10); }

  virtual task body();
    temp_data = new[8];
    temp_data[0] = data0; temp_data[1] = data1;
    temp_data[2] = data2; temp_data[3] = data3;
    temp_data[4] = data0; temp_data[5] = data1;
    temp_data[6] = data2; temp_data[7] = data3;
    `ovm_do_with(this_transfer, 
      { addr == start_addr;
        read_write == WRITE;
        size == 8;
        foreach (data[i]) data[i] == temp_data[i];
        error_pos == 1000;
        transmit_delay == transmit_del; } )
    `message(OVM_HIGH,("Writing : addr = `x%0h, data[0] = `x%0h, \
      data[1] = `x%0h, data[2] = `x%0h, data[3] = `x%0h, data[4] = `x%0h, \
      data[5] = `x%0h, data[6] = `x%0h, data[7] = `x%0h",
      this_transfer.addr, this_transfer.data[0],
      this_transfer.data[1], this_transfer.data[2],
      this_transfer.data[3], this_transfer.data[4],
      this_transfer.data[5], this_transfer.data[6],
      this_transfer.data[7]))
  endtask

endclass : write_double_word_seq

`endif // XBUS_MASTER_SEQ_LIB_SV