xbus_tb_top.sv

Open Verification Methodology

// $Id: //dvt/vtech/dev/main/ovm/examples/xbus/examples/xbus_tb_top.sv#5 $
//----------------------------------------------------------------------
//   Copyright 2007-2008 Mentor Graphics Corporation
//   Copyright 2007-2008 Cadence Design Systems, Inc.
//   All Rights Reserved Worldwide
//
//   Licensed under the Apache License, Version 2.0 (the
//   "License"); you may not use this file except in
//   compliance with the License.  You may obtain a copy of
//   the License at
//
//       http://www.apache.org/licenses/LICENSE-2.0
//
//   Unless required by applicable law or agreed to in
//   writing, software distributed under the License is
//   distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//   CONDITIONS OF ANY KIND, either express or implied.  See
//   the License for the specific language governing
//   permissions and limitations under the License.
//----------------------------------------------------------------------

`define XBUS_ADDR_WIDTH 16

`include "dut_dummy.v"
`include "xbus_if.sv"

module xbus_tb_top;

  `include "ovm_macros.svh"
  `include "xbus.svh"
  `include "test_lib.sv"

  xbus_if xi0();
  
  reg xbus_clock;
  reg xbus_reset;
  wire [15:0] xbus_addr;
  wire [1:0] xbus_size;
  wire xbus_read;
  wire xbus_write;
  reg xbus_start;
  wire xbus_bip;
  wire [7:0] xbus_data;
  wire xbus_wait;
  wire xbus_error;
  reg xbus_req_master0;
  reg xbus_gnt_master0;
  reg xbus_req_master1;
  reg xbus_gnt_master1;

  dut_dummy dut(
    xbus_req_master0,
    xbus_gnt_master0,
    xbus_req_master1,
    xbus_gnt_master1,
    xbus_clock,
    xbus_reset,
    xbus_addr,
    xbus_size,
    xbus_read,
    xbus_write,
    xbus_start,
    xbus_bip,
    xbus_data,
    xbus_wait,
    xbus_error
  );

  // Interface Connections
  assign xi0.sig_clock = xbus_clock;
  assign xi0.sig_reset = xbus_reset;

  assign xbus_req_master0 = xi0.sig_request[0];
  assign xi0.sig_grant[0] = xbus_gnt_master0;
  assign xbus_req_master1 = xi0.sig_request[1];
  assign xi0.sig_grant[1] = xbus_gnt_master1;

  assign xbus_addr = xi0.sig_addr;
  assign xbus_size = xi0.sig_size;
  assign xbus_read = xi0.sig_read;
  assign xbus_write = xi0.sig_write;
  assign xi0.sig_start = xbus_start;
  assign xbus_bip = xi0.sig_bip;

  assign xi0.sig_data = xbus_data;

  assign xbus_wait = xi0.sig_wait;
  assign xbus_error = xi0.sig_error;

  assign xbus_data = xi0.rw ? xi0.sig_data_out : 8'bz;

  initial begin
    run_test();
  end

  initial begin
    xbus_reset <= 1'b1;
    xbus_clock <= 1'b1;
    #51 xbus_reset = 1'b0;
  end

  //Generate Clock
  always
    #5 xbus_clock = ~xbus_clock;

endmodule