📄 sdram.c
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#include <stdio.h>
#include <csl.h>
#include <csl_irq.h>
#include <csl_chip.h>
#include <csl_emifa.h>
/* Flash address definitions */
#define EVMDM642_FLASH_BASE 0x90000000
#define EVMDM642_FLASH_SECTORSIZE 0x010000 //64k
#define EVMDM642_FLASH_SECTORS 0x40 //0x8 64
#define EVMDM642_FLASH_PAGES 0x8
#define EVMDM642_FLASH_PAGESIZE 0x080000 //512k
#define EVMDM642_FLASH_SIZE 0x400000 //4M
#define EVMDM642_FLASH_CTL555 (EVMDM642_FLASH_BASE + 0x555)
#define EVMDM642_FLASH_CTLAAA (EVMDM642_FLASH_BASE + 0xaaa)
#define EVMDM642_FLASH_SUPPORT 1
static EMIFA_Config MyEmifaConfig =
{
EMIFA_GBLCTL_RMK
(
EMIFA_GBLCTL_EK2RATE_FULLCLK, //1 X EMIF input clock
EMIFA_GBLCTL_EK2HZ_CLK, //eclkout2 continue output during hold
EMIFA_GBLCTL_EK2EN_ENABLE, //eclkout2 enable output
EMIFA_GBLCTL_BRMODE_MRSTATUS, //bus request is memory access or refresh pending/in progress
EMIFA_GBLCTL_NOHOLD_DISABLE,
EMIFA_GBLCTL_EK1HZ_CLK, //eclkout1 continue output during hold
EMIFA_GBLCTL_EK1EN_ENABLE, //eclkout1 enable output
EMIFA_GBLCTL_CLK4EN_ENABLE, //clkout4 output enable
EMIFA_GBLCTL_CLK6EN_ENABLE //clkout6 output enable
),
0xffffffd3, //64BIT SDRAM
// 0xffffff33, //32BIT SDRAM
// 0xffffff93, //16bit SDRAM
// 0xffffff83, //8bit SDRAM
0xffffff03,
0x22a28a22,
0x22a28a22,
EMIFA_SDCTL_RMK
(
EMIFA_SDCTL_SDBSZ_4BANKS, //SDRAM bank size 4 banks
EMIFA_SDCTL_SDRSZ_12ROW, //row number = 12
EMIFA_SDCTL_SDCSZ_8COL, //column number = 8
EMIFA_SDCTL_RFEN_ENABLE, //SDRAM refresh enable
//EMIFA_SDCTL_INIT_NO, //SDRAM 配置完每个CE空间后，不初始化
EMIFA_SDCTL_INIT_YES, //SDRAM 配置完每个CE空间后，初始化
EMIFA_SDCTL_TRCD_OF(2), //TRCD = (Trcd / Tcyc) - 1
EMIFA_SDCTL_TRP_OF(2), //TRP = (Trp / Tcyc) - 1
EMIFA_SDCTL_TRC_OF(8),
EMIFA_SDCTL_SLFRFR_DISABLE //self refresh mode disable
),
EMIFA_SDTIM_RMK
(
EMIFA_SDTIM_XRFR_DEFAULT, //EXT TIMER default
EMIFA_SDTIM_PERIOD_OF(2083) //refresh period,clockout1 = 10ns
),
EMIFA_SDEXT_RMK
(
EMIFA_SDEXT_WR2RD_OF(0), //cycles between write to read command = 1,subtract 1 is 0
EMIFA_SDEXT_WR2DEAC_OF(1), //cycles between write to precharge = 2
EMIFA_SDEXT_WR2WR_OF(1), //cycles between write to write = 2
EMIFA_SDEXT_R2WDQM_OF(1), //cycles between read to bex = 2
EMIFA_SDEXT_RD2WR_OF(0), //cycles between read to write = 1
EMIFA_SDEXT_RD2DEAC_OF(1), //
EMIFA_SDEXT_RD2RD_OF(0), //
EMIFA_SDEXT_THZP_OF(2), //Troh = 3 cycle
EMIFA_SDEXT_TWR_OF(1), //Twr = 1 clock +6 ns
EMIFA_SDEXT_TRRD_OF(0), //Trrd = 12ns
EMIFA_SDEXT_TRAS_OF(5), //Tras = 42ns
EMIFA_SDEXT_TCL_OF(1) //cas latency = 3 clock
),
0x00000002,
0x00000002,
0x00000002,
0x00000002
};
//volatile Uint32* SDRAM_FIRST_ADDRESS = (volatile Uint32 *) 0x80000000;
#pragma DATA_SECTION(sdram_data,".off_ram");
unsigned int sdram_data[0x10000];
extern far void vectors();
unsigned char FlashTestChar[10] ;
void EVMDM642_FLASH_write(Uint32 src, Uint32 dst, Uint32 length)
{
Uint8 *psrc, *pdst;
Uint32 i;
/* Establish source and destination */
psrc = (Uint8 *)src;
pdst = (Uint8 *)dst;
for (i = 0; i < length; i++)
{
// Program one 8-bit word
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xaa;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x55;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xa0;
*pdst = *psrc;
// Wait for operation to complete
while(1)
if (*pdst == *psrc)
break;
pdst++;
psrc++;
}
/* Put back in read mode */
*((Uint16 *)EVMDM642_FLASH_BASE) = 0xf0;
}
void EVMDM642_FLASH_read(Uint32 src, Uint32 dst, Uint32 length)
{
Uint8 *psrc, *pdst;
Uint32 i;
/* Establish source and destination */
psrc = (Uint8 *)src;
pdst = (Uint8 *)dst;
for (i = 0; i < length; i++)
{
*pdst++ = *psrc++;
}
}
/* Constant table containing end address of each sector */
static Uint32 sector_end[EVMDM642_FLASH_SECTORS] = {
EVMDM642_FLASH_BASE + 0x00ffff, /* Sector 0 */
EVMDM642_FLASH_BASE + 0x01ffff, /* Sector 1 */
EVMDM642_FLASH_BASE + 0x02ffff, /* Sector 2 */
EVMDM642_FLASH_BASE + 0x03ffff, /* Sector 3 */
EVMDM642_FLASH_BASE + 0x04ffff, /* Sector 4 */
EVMDM642_FLASH_BASE + 0x05ffff, /* Sector 5 */
EVMDM642_FLASH_BASE + 0x06ffff, /* Sector 6 */
EVMDM642_FLASH_BASE + 0x07ffff /* Sector 7 */
};
/* Erase a segment of Flash memory */
void EVMDM642_FLASH_erase(Uint32 start, Uint32 length)
{
Int16 i;
Uint8 *pdata;
Uint32 sector_base, end;
/* Calculate extents of range to erase */
end = start + length - 1;
/* Walk through each sector, erase any sectors within range */
sector_base = EVMDM642_FLASH_BASE;
for (i = 0; i < EVMDM642_FLASH_SECTORS; i++)
{
if ( ( ( sector_base >= start ) || ( sector_end[i] >= start ) ) &&
( ( sector_base <= end ) || ( sector_end[i] <= end ) ) )
{
/* Start sector erase sequence */
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xaa;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x55;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x80;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xaa;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x55;
/* Start erase at sector address */
pdata = (Uint8 *)sector_base;
*pdata = 0x30;
/* Wait for erase to complete */
while (1)
if (*pdata & 0x80)
break;
/* Put back in read mode */
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xf0;
}
/* Advance to next sector */
sector_base = sector_end[i] + 1;
}
}
/* Calculate the checksum of a data range in Flash */
Uint32 EVMDM642_FLASH_checksum(Uint32 start, Uint32 length)
{
Int16 i;
Uint8 *pdata;
Uint32 checksum;
/* Establish source and destination */
pdata = (Uint8 *)start;
/* Calculate checksum by adding each word to the total */
checksum = 0;
for (i = 0; i < length; i++)
{
checksum += *pdata++;
}
return checksum;
}
//zhoaic
void Flash_ID()
{
Uint8 t1,t2;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xaa;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x55;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x90;
t1 = *((Uint8 *)EVMDM642_FLASH_BASE);
t2 = *((Uint8 *)(EVMDM642_FLASH_BASE+1));
// prin("MID:0x");
// puts((const char*)t1);
// puts("\n");
printf("MID:0x%x\n",t1);
printf("DID:0x%x\n",t2);
}
void Flash_Wtest()
{
Uint8 i;
for(i=0;i<200;i++)
{
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xaa;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x55;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xa0;
*((Uint8 *)(EVMDM642_FLASH_BASE+i)) = i;
while(1)
if (*((Uint8 *)(EVMDM642_FLASH_BASE+i)) == i)
break;
}
}
void main()
{
// Copy 256 16-bit words from buf to the beginning of Flash
Uint16 buf[8];
Uint8 temp,i;
//初始化CSL
CSL_init();
//配置EMIFA
//EMIFA_config(&MyEmifaConfig);
// IRQ_setVecs(vectors);
// IRQ_nmiEnable();
//IRQ_globalEnable();
// buf[0] = 0x00;
// *((Uint8 *)EVMDM642_FLASH_BASE) = 0xf0;
while(1)
// EVMDM642_FLASH_erase(0x90000000,200);
// Flash_Wtest();
Flash_ID();
while(1){
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x00;
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
buf[0] = 0x00;
buf[1] = 0x01;
// }
// EVMDM642_FLASH_erase(EVMDM642_FLASH_BASE, 256);
EVMDM642_FLASH_write((Uint32)buf, EVMDM642_FLASH_BASE, 4);
}
/*
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xaa;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x55;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xa0;
*((Uint8 *)EVMDM642_FLASH_BASE) = 0x00;
//*((Uint8 *)EVMDM642_FLASH_BASE) = 0x55;
//*((Uint8 *)EVMDM642_FLASH_BASE) = 0x10;
for(i=0;i<10;i++);
*((Uint8 *)EVMDM642_FLASH_BASE) = 0xf0;
*/
for(i=0;i<10;i++)
{
temp = *((Uint8 *)(EVMDM642_FLASH_BASE + i)) ;
}
while(1);
}
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