📄 lesson1.lst
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__text_start:
__start:
0047 EFCF LDI R28,0xFF
0048 E1D0 LDI R29,0x10
0049 BFCD OUT 0x3D,R28
004A BFDE OUT 0x3E,R29
004B 51C0 SUBI R28,0x10
004C 40D0 SBCI R29,0
004D EA0A LDI R16,0xAA
004E 8308 STD Y+0,R16
004F 2400 CLR R0
0050 E0E1 LDI R30,1
0051 E0F1 LDI R31,1
0052 E011 LDI R17,1
0053 30E2 CPI R30,2
0054 07F1 CPC R31,R17
0055 F011 BEQ 0x0058
0056 9201 ST R0,Z+
0057 CFFB RJMP 0x0053
0058 8300 STD Z+0,R16
0059 E8EC LDI R30,0x8C
005A E0F0 LDI R31,0
005B E0A0 LDI R26,0
005C E0B1 LDI R27,1
005D E010 LDI R17,0
005E 38ED CPI R30,0x8D
005F 07F1 CPC R31,R17
0060 F021 BEQ 0x0065
0061 95C8 LPM
0062 9631 ADIW R30,1
0063 920D ST R0,X+
0064 CFF9 RJMP 0x005E
0065 940E00DF CALL _main
_exit:
0067 CFFF RJMP _exit
_delay:
i --> R20
j --> R22
ms --> R16
0068 940E0197 CALL push_gset2
FILE: C:\icc\examples.avr\lesson1\lesson1.c
(0001) #include <iom128v.h>
(0002) #include <macros.h>
(0003) #define uchar unsigned char
(0004) #define uint unsigned int
(0005)
(0006) #define mclk 7372800
(0007) #pragma interrupt_handler uart_rx:31
(0008) uchar rdata,flag=0;
(0009) void delay(uint ms)
(0010) {
(0011) uint i,j;
(0012) for(i=0;i<ms;i++)
006A 2744 CLR R20
006B 2755 CLR R21
006C C00B RJMP 0x0078
(0013) {
(0014) for(j=0;j<562;j++);
006D 2766 CLR R22
006E 2777 CLR R23
006F C002 RJMP 0x0072
0070 5F6F SUBI R22,0xFF
0071 4F7F SBCI R23,0xFF
0072 3362 CPI R22,0x32
0073 E0E2 LDI R30,2
0074 077E CPC R23,R30
0075 F3D0 BCS 0x0070
0076 5F4F SUBI R20,0xFF
0077 4F5F SBCI R21,0xFF
0078 1740 CP R20,R16
0079 0751 CPC R21,R17
007A F390 BCS 0x006D
007B 940E018B CALL pop_gset2
007D 9508 RET
(0015) }
(0016) }
(0017) void init_port();
(0018) void init_port()
(0019) {
(0020) DDRB=DDRB|BIT(7);
_init_port:
007E 9ABF SBI 0x17,7
(0021) PORTB=PORTB|BIT(7);
007F 9AC7 SBI 0x18,7
0080 9508 RET
_uart_init:
baud --> R10
0081 940E0195 CALL push_gset3
0083 0158 MOVW R10,R16
(0022)
(0023) }
(0024) void uart_init(uint baud)
(0025) {
(0026) UCSR1B=0x00;
0084 2422 CLR R2
0085 9220009A STS 0x9A,R2
(0027) UCSR1A=0x00; //控制寄存器清零
0087 9220009B STS 0x9B,R2
(0028) UCSR1C=(0<<UPM10)|(3<<UCSZ10);
0089 E086 LDI R24,6
008A 9380009D STS 0x9D,R24
(0029) //选择UCSRC，异步模式，禁止
(0030) // 校验，1位停止位，8位数据位
(0031) baud=mclk/16/baud-1 ; //波特率最大为65K
008C 0115 MOVW R2,R10
008D 2444 CLR R4
008E 2455 CLR R5
008F E040 LDI R20,0
0090 E058 LDI R21,0x8
0091 E067 LDI R22,7
0092 E070 LDI R23,0
0093 925A ST R5,-Y
0094 924A ST R4,-Y
0095 923A ST R3,-Y
0096 922A ST R2,-Y
0097 018A MOVW R16,R20
0098 019B MOVW R18,R22
0099 940E0120 CALL div32s
009B E041 LDI R20,1
009C E050 LDI R21,0
009D E060 LDI R22,0
009E E070 LDI R23,0
009F 0118 MOVW R2,R16
00A0 0129 MOVW R4,R18
00A1 1A24 SUB R2,R20
00A2 0A35 SBC R3,R21
00A3 0A46 SBC R4,R22
00A4 0A57 SBC R5,R23
00A5 0151 MOVW R10,R2
(0032) UBRR1L=baud;
00A6 92A00099 STS 0x99,R10
(0033) UBRR1H=baud>>8; //设置波特率
00A8 2C23 MOV R2,R3
00A9 2433 CLR R3
00AA 92200098 STS 0x98,R2
(0034) UCSR1B=(1<<TXEN1)|(1<<RXEN1)|(1<<RXCIE1);
00AC E988 LDI R24,0x98
00AD 9380009A STS 0x9A,R24
(0035) //接收、发送使能，接收中断使能
(0036) SREG=BIT(7); //全局中断开放
00AF E880 LDI R24,0x80
00B0 BF8F OUT 0x3F,R24
(0037) DDRD|=0X08; //配置TX为输出（很重要）
00B1 9A8B SBI 0x11,3
00B2 940E018E CALL pop_gset3
00B4 9508 RET
(0038)
(0039) }
(0040) void uart_sendB(uchar data)
(0041) {
(0042) while(!(UCSR1A&(BIT(UDRE1)))) ;
_uart_sendB:
data --> R16
00B5 9020009B LDS R2,0x9B
00B7 FE25 SBRS R2,5
00B8 CFFC RJMP _uart_sendB
(0043) UDR1=data;
00B9 9300009C STS 0x9C,R16
(0044) while(!(UCSR1A&(BIT(TXC1))));
00BB 9020009B LDS R2,0x9B
00BD FE26 SBRS R2,6
00BE CFFC RJMP 0x00BB
(0045) UCSR1A|=BIT(TXC1);
00BF 9180009B LDS R24,0x9B
00C1 6480 ORI R24,0x40
00C2 9380009B STS 0x9B,R24
00C4 9508 RET
_uart_rx:
00C5 922A ST R2,-Y
00C6 938A ST R24,-Y
00C7 B62F IN R2,0x3F
00C8 922A ST R2,-Y
(0046) }
(0047) void uart_rx()
(0048) {
(0049) UCSR1B&=~BIT(RXCIE1);
00C9 9180009A LDS R24,0x9A
00CB 778F ANDI R24,0x7F
00CC 9380009A STS 0x9A,R24
(0050) rdata=UDR1;
00CE 9020009C LDS R2,0x9C
00D0 92200101 STS rdata,R2
(0051) flag=1;
00D2 E081 LDI R24,1
00D3 93800100 STS flag,R24
(0052) UCSR1B|=BIT(RXCIE1);
00D5 9180009A LDS R24,0x9A
00D7 6880 ORI R24,0x80
00D8 9380009A STS 0x9A,R24
00DA 9029 LD R2,Y+
00DB BE2F OUT 0x3F,R2
00DC 9189 LD R24,Y+
00DD 9029 LD R2,Y+
00DE 9518 RETI
(0053) }
(0054) void main()
(0055) {
(0056) unsigned char j='a';
_main:
i --> R22
j --> R20
00DF E641 LDI R20,0x61
(0057)
(0058) unsigned int i=3;
00E0 E063 LDI R22,3
00E1 E070 LDI R23,0
(0059)
(0060) //
(0061) //
(0062) // init_port();
(0063) uart_init(19200);
00E2 E000 LDI R16,0
00E3 E41B LDI R17,0x4B
00E4 DF9C RCALL _uart_init
(0064) delay(1);
00E5 E001 LDI R16,1
00E6 E010 LDI R17,0
00E7 DF80 RCALL _delay
(0065) uart_sendB(i);
00E8 2F06 MOV R16,R22
00E9 DFCB RCALL _uart_sendB
(0066) delay(1);
00EA E001 LDI R16,1
00EB E010 LDI R17,0
00EC DF7B RCALL _delay
(0067) uart_sendB(j);
00ED 2F04 MOV R16,R20
00EE DFC6 RCALL _uart_sendB
(0068) uart_sendB(i);
00EF 2F06 MOV R16,R22
00F0 DFC4 RCALL _uart_sendB
(0069) delay(1);
00F1 E001 LDI R16,1
00F2 E010 LDI R17,0
00F3 DF74 RCALL _delay
(0070) uart_sendB(j);
00F4 2F04 MOV R16,R20
00F5 DFBF RCALL _uart_sendB
(0071)
(0072) uart_sendB(i);
00F6 2F06 MOV R16,R22
00F7 DFBD RCALL _uart_sendB
(0073) delay(1);
00F8 E001 LDI R16,1
00F9 E010 LDI R17,0
00FA DF6D RCALL _delay
(0074) uart_sendB(j);
00FB 2F04 MOV R16,R20
00FC DFB8 RCALL _uart_sendB
(0075)
(0076) uart_sendB(i);
00FD 2F06 MOV R16,R22
00FE DFB6 RCALL _uart_sendB
(0077) delay(1);
00FF E001 LDI R16,1
0100 E010 LDI R17,0
0101 DF66 RCALL _delay
(0078) uart_sendB(j);
0102 2F04 MOV R16,R20
0103 DFB1 RCALL _uart_sendB
(0079)
(0080) uart_sendB(i);
0104 2F06 MOV R16,R22
0105 DFAF RCALL _uart_sendB
(0081) delay(1);
0106 E001 LDI R16,1
0107 E010 LDI R17,0
0108 DF5F RCALL _delay
(0082) uart_sendB(j);
0109 2F04 MOV R16,R20
010A DFAA RCALL _uart_sendB
(0083)
(0084) uart_sendB(i);
010B 2F06 MOV R16,R22
010C DFA8 RCALL _uart_sendB
(0085) delay(1);
010D E001 LDI R16,1
010E E010 LDI R17,0
010F DF58 RCALL _delay
(0086) uart_sendB(j);
0110 2F04 MOV R16,R20
0111 DFA3 RCALL _uart_sendB
(0087)
(0088)
(0089) uart_sendB(i);
0112 2F06 MOV R16,R22
0113 DFA1 RCALL _uart_sendB
(0090) delay(1);
0114 E001 LDI R16,1
0115 E010 LDI R17,0
0116 DF51 RCALL _delay
(0091) uart_sendB(j);
FILE: <library>
0117 2F04 MOV R16,R20
0118 DF9C RCALL _uart_sendB
0119 9508 RET
div32u:
011A 94E8 BCLR 6
011B C001 RJMP 0x011D
mod32u:
011C 9468 BSET 6
011D D02F RCALL long_div_prolog
011E 24CC CLR R12
011F C008 RJMP 0x0128
div32s:
0120 94E8 BCLR 6
0121 C001 RJMP 0x0123
mod32s:
0122 9468 BSET 6
0123 D029 RCALL long_div_prolog
0124 FD37 SBRC R19,7
0125 D053 RCALL neg_R16_R19
0126 FDB7 SBRC R27,7
0127 D05A RCALL neg_R24_R27
0128 2477 CLR R7
0129 2488 CLR R8
012A 2499 CLR R9
012B 24AA CLR R10
012C 24BB CLR R11
012D D041 RCALL tst_R16_R19
012E F0C1 BEQ 0x0147
012F D044 RCALL tst_R24_R27
0130 F0B1 BEQ 0x0147
0131 E2E8 LDI R30,0x28
0132 0F00 LSL R16
0133 1F11 ROL R17
0134 1F22 ROL R18
0135 1F33 ROL R19
0136 1C77 ROL R7
0137 1C88 ROL R8
0138 1C99 ROL R9
0139 1CAA ROL R10
013A 1CBB ROL R11
013B 1688 CP R8,R24
013C 0699 CPC R9,R25
013D 06AA CPC R10,R26
013E 06BB CPC R11,R27
013F F028 BCS 0x0145
0140 1A88 SUB R8,R24
0141 0A99 SBC R9,R25
0142 0AAA SBC R10,R26
0143 0ABB SBC R11,R27
0144 9503 INC R16
0145 95EA DEC R30
0146 F759 BNE 0x0132
0147 F426 BRTC 0x014C
0148 2D08 MOV R16,R8
0149 2D19 MOV R17,R9
014A 2D2A MOV R18,R10
014B 2D3B MOV R19,R11
014C C013 RJMP long_div_epilog
long_div_prolog:
014D 927A ST R7,-Y
014E 928A ST R8,-Y
014F 929A ST R9,-Y
0150 92AA ST R10,-Y
0151 92BA ST R11,-Y
0152 92CA ST R12,-Y
0153 93EA ST R30,-Y
0154 938A ST R24,-Y
0155 939A ST R25,-Y
0156 93AA ST R26,-Y
0157 93BA ST R27,-Y
0158 858B LDD R24,Y+11
0159 859C LDD R25,Y+12
015A 85AD LDD R26,Y+13
015B 85BE LDD R27,Y+14
015C 2EC3 MOV R12,R19
015D F00E BRTS 0x015F
015E 26CB EOR R12,R27
015F 9508 RET
long_div_epilog:
0160 FCC7 SBRC R12,7
0161 D017 RCALL neg_R16_R19
0162 91B9 LD R27,Y+
0163 91A9 LD R26,Y+
0164 9199 LD R25,Y+
0165 9189 LD R24,Y+
0166 91E9 LD R30,Y+
0167 90C9 LD R12,Y+
0168 90B9 LD R11,Y+
0169 90A9 LD R10,Y+
016A 9099 LD R9,Y+
016B 9089 LD R8,Y+
016C 9079 LD R7,Y+
016D 9624 ADIW R28,4
016E 9508 RET
tst_R16_R19:
016F 2FE0 MOV R30,R16
0170 2BE1 OR R30,R17
0171 2BE2 OR R30,R18
0172 2BE3 OR R30,R19
0173 9508 RET
tst_R24_R27:
0174 2FE8 MOV R30,R24
0175 2BE9 OR R30,R25
0176 2BEA OR R30,R26
0177 2BEB OR R30,R27
0178 9508 RET
neg_R16_R19:
0179 9500 COM R16
017A 9510 COM R17
017B 9520 COM R18
017C 9530 COM R19
017D 5F0F SUBI R16,0xFF
017E 4F1F SBCI R17,0xFF
017F 4F2F SBCI R18,0xFF
0180 4F3F SBCI R19,0xFF
0181 9508 RET
neg_R24_R27:
0182 9580 COM R24
0183 9590 COM R25
0184 95A0 COM R26
0185 95B0 COM R27
0186 5F8F SUBI R24,0xFF
0187 4F9F SBCI R25,0xFF
0188 4FAF SBCI R26,0xFF
0189 4FBF SBCI R27,0xFF
018A 9508 RET
pop_gset2:
018B E0E2 LDI R30,2
018C 940C019D JMP pop
pop_gset3:
018E E0E4 LDI R30,4
018F 940C019D JMP pop
push_gset5:
0191 92FA ST R15,-Y
0192 92EA ST R14,-Y
push_gset4:
0193 92DA ST R13,-Y
0194 92CA ST R12,-Y
push_gset3:
0195 92BA ST R11,-Y
0196 92AA ST R10,-Y
push_gset2:
0197 937A ST R23,-Y
0198 936A ST R22,-Y
push_gset1:
0199 935A ST R21,-Y
019A 934A ST R20,-Y
019B 9508 RET
pop_gset1:
019C E0E1 LDI R30,1
pop:
019D 9149 LD R20,Y+
019E 9159 LD R21,Y+
019F FDE0 SBRC R30,0
01A0 9508 RET
01A1 9169 LD R22,Y+
01A2 9179 LD R23,Y+
01A3 FDE1 SBRC R30,1
01A4 9508 RET
01A5 90A9 LD R10,Y+
01A6 90B9 LD R11,Y+
01A7 FDE2 SBRC R30,2
01A8 9508 RET
01A9 90C9 LD R12,Y+
01AA 90D9 LD R13,Y+
01AB FDE3 SBRC R30,3
01AC 9508 RET
01AD 90E9 LD R14,Y+
01AE 90F9 LD R15,Y+
01AF 9508 RET
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