dec5502_dma.c

DEC5502_USB程序主要实现了与PC机应用程序之间的USB通讯

/******************************************************************************/
/*  Copyright 2004 by SEED Electronic Technology LTD.                         */
/*  All rights reserved. SEED Electronic Technology LTD.                      */
/*  Restricted rights to use, duplicate or disclose this code are             */
/*  granted through contract.                                                 */
/*                                                                            */
/*                                                                            */
/******************************************************************************/
/*----------------------------------------------------------------------------*/
/* MODULE NAME... DMA														  */
/* FILENAME...... DEC5502_DMA.c											  	  */
/* DATE CREATED.. Wed 6/11/2004 											  */
/* PROJECT....... Data transifer between DARAM and SDRAM through DMA channel  */
/* COMPONENT..... 															  */
/* PREREQUISITS.. 															  */
/*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------*/
/* DESCRIPTION:  															  */
/*   																		  */
/* This is an example for DMA operaton of C5502								  */
/*----------------------------------------------------------------------------*/

#include <stdio.h>
#include <csl.h>
#include <csl_irq.h>
#include <csl_dma.h>
#include <csl_emif.h>
#include <csl_emifBhal.h>

#include <csl_gpt.h>

/* Constant defines transfer length */
#define FrameLength      3000
#define ElementLength	 4
#define DataLength 		 FrameLength*ElementLength

/* Place SrcData and DstData of DMA transfer in seperate memory section	 */
/* to better control placement in user specified memory range  			 */
#pragma DATA_SECTION(SrcData,"SrcDataMem")
Uint16 SrcData[DataLength];
    
#pragma DATA_SECTION(DstData, "DstDataMem")
Uint16 DstData[DataLength];

/* Define macro to access Timer 0 memory-mapped count registers */
#define MYGPTCINT1_0 (*(volatile ioport Uint16*)(0x1008))
#define MYGPTCINT2_0 (*(volatile ioport Uint16*)(0x1009))
#define MYGPTCINT3_0 (*(volatile ioport Uint16*)(0x100A))
#define MYGPTCINT4_0 (*(volatile ioport Uint16*)(0x100B))

/* This example effects a single-frame transfer of 3600     */
/* elements from SDRAM to DARAM, via DMA                    */
/* The macro invocation reflect the settings required in    */
/* DMA control registers to make this happen.               */                             
/*   DMACSDP       dstben    == 2                           */
/*                 dstpack   == 1                           */
/*                 dst       == 0                           */
/*                 srcben    == 2                           */
/*                 srcpack   == 1                           */
/*                 src       == 2                           */
/*                 datatype  == 2                           */
/*                                                          */
/*   DMACCR        dstamode  == 1                           */
/*                 srcamode  == 1                           */
/*                 endprog   == 0                           */
/*                 repeat    == 0                           */ 
/*                 autoinit  == 0                           */
/*                 en        == 0                           */
/*                 prio      == 0                           */
/*                 fs        == 0                           */
/*                 sync      == 0                           */
/*                                                          */
/*  DMACICR        blockie   == 1                           */
/*                 lastie    == 1                           */
/*                 frameie   == 1                           */
/*                 firsthalfie == 1                         */
/*                 dropie    == 1                           */
/*                 timeoutie == 1                           */

DMA_Config  MyConfig = { 
  DMA_DMACSDP_RMK(
    DMA_DMACSDP_SRCBEN_BURST4,				//DMA_DMACSDP_SRCBEN_BURST4 2 DMA_DMACSDP_DSTBEN_NOBURST
    DMA_DMACSDP_SRCPACK_ON,					//DMA_DMACSDP_SRCPACK_ON  1 DMA_DMACSDP_DSTPACK_OFF
    DMA_DMACSDP_DST_DARAM,			
    DMA_DMACSDP_SRCBEN_BURST4,				//DMA_DMACSDP_SRCBEN_BURST4 2DMA_DMACSDP_SRCBEN_NOBURST
    DMA_DMACSDP_SRCPACK_ON,					//DMA_DMACSDP_SRCPACK_ON 1 DMA_DMACSDP_SRCPACK_OFF
    DMA_DMACSDP_SRC_EMIF,					/* SDRAM 	*/
    DMA_DMACSDP_DATATYPE_32BIT				/* 32bits 	*/
  ),                                    	/* DMACSDP 	*/
  DMA_DMACCR_RMK(
    DMA_DMACCR_DSTAMODE_POSTINC,
    DMA_DMACCR_SRCAMODE_POSTINC,
    DMA_DMACCR_ENDPROG_OFF,
    DMA_DMACCR_REPEAT_OFF,
    DMA_DMACCR_AUTOINIT_OFF,
    DMA_DMACCR_EN_STOP,
    DMA_DMACCR_PRIO_HI,
    DMA_DMACCR_FS_ENABLE,
    DMA_DMACCR_SYNC_NONE
  ),                                       	/* DMACCR   */
  DMA_DMACICR_RMK(
    DMA_DMACICR_BLOCKIE_OFF,
    DMA_DMACICR_LASTIE_OFF,
    DMA_DMACICR_FRAMEIE_ON,
    DMA_DMACICR_FIRSTHALFIE_OFF,
    DMA_DMACICR_DROPIE_OFF,
    DMA_DMACICR_TIMEOUTIE_OFF
  ),                                       	/* DMACICR  */
    (DMA_AdrPtr) &SrcData,              	/* DMACSSAL */
    0,                         				/* DMACSSAU */
    (DMA_AdrPtr) &DstData,              	/* DMACDSAL */
    0,                         				/* DMACDSAU */
    FrameLength,                            /* DMACEN   */
    ElementLength,                          /* DMACFN   */
    0,                                     	/* DMACFI   */
    0,                                     	/* DMACEI   */
    0,								/* DMA Channel Destination Frame Index Register */
    0     							/* DMA Channel Destination Element Index */
};

/*SDRAM的EMIF设置*/
EMIF_Config MyEmifConfig = {
EMIF_GBLCTL1_RMK(					// EMIF Global Control Register 1
  EMIF_GBLCTL1_NOHOLD_HOLD_ENABLED,	// Hold enable
  EMIF_GBLCTL1_EK1HZ_EK1EN,			// High-Z control
  EMIF_GBLCTL1_EK1EN_ENABLED		// ECLKOUT1 Enable
  ),
EMIF_GBLCTL2_RMK(					// EMIF Global Control Register 2
  EMIF_GBLCTL2_EK2RATE_1XCLK,		// ECLKOUT2 Rate
  EMIF_GBLCTL2_EK2HZ_EK2EN,			// EK2HZ = 0, ECLKOUT2 is driven with value specified by EKnEN during
  EMIF_GBLCTL2_EK2EN_ENABLED		// ECLKOUT2 Enable (enabled by default)
  ), 
EMIF_CE1CTL1_RMK(					// CE1 Space Control Register 1
  EMIF_CE1CTL1_TA_DEFAULT,
  EMIF_CE1CTL1_READ_STROBE_DEFAULT,
  EMIF_CE1CTL1_MTYPE_DEFAULT,
  EMIF_CE1CTL1_WRITE_HOLD_MSB_DEFAULT,
  EMIF_CE1CTL1_READ_HOLD_DEFAULT
  ),
EMIF_CE1CTL2_RMK(					// CE1 Space Control Register 2
  EMIF_CE1CTL2_WRITE_SETUP_DEFAULT,
  EMIF_CE1CTL2_WRITE_STROBE_DEFAULT,
  EMIF_CE1CTL2_WRITE_HOLD_DEFAULT,
  EMIF_CE1CTL2_READ_SETUP_DEFAULT
  ),
EMIF_CE0CTL1_RMK(					// CE0 Space Control Register 1
  EMIF_CE0CTL1_TA_DEFAULT,
  EMIF_CE0CTL1_READ_STROBE_DEFAULT,
  EMIF_CE0CTL1_MTYPE_DEFAULT,
  EMIF_CE0CTL1_WRITE_HOLD_MSB_DEFAULT,
  EMIF_CE0CTL1_READ_HOLD_DEFAULT
  ),
EMIF_CE0CTL2_RMK(					// CE0 Space Control Register 2
  EMIF_CE0CTL2_WRITE_SETUP_DEFAULT,
  EMIF_CE0CTL2_WRITE_STROBE_DEFAULT,
  EMIF_CE0CTL2_WRITE_HOLD_DEFAULT,
  EMIF_CE0CTL2_READ_SETUP_DEFAULT
  ),
EMIF_CE2CTL1_RMK(					// CE2 Space Control Register 1
  EMIF_CE2CTL1_TA_DEFAULT,			// Not use for SDRAM (asynchronous memory types only)
  EMIF_CE2CTL1_READ_STROBE_DEFAULT,	// Read strobe width
  EMIF_CE2CTL1_MTYPE_32BIT_SDRAM,	// 32-bit-wide SDRAM
  EMIF_CE2CTL1_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE2CTL1_READ_HOLD_DEFAULT	// Read hold width
  ),
EMIF_CE2CTL2_RMK(					// CE2 Space Control Register 2
  EMIF_CE2CTL2_WRITE_SETUP_DEFAULT,	// Write setup width
  EMIF_CE2CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
  EMIF_CE2CTL2_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE2CTL2_READ_SETUP_DEFAULT	// Read setup width
  ),
EMIF_CE3CTL1_RMK(					// CE3 Space Control Register 1
  EMIF_CE3CTL1_TA_DEFAULT,			// Not use for SDRAM (asynchronous memory types only)
  EMIF_CE3CTL1_READ_STROBE_DEFAULT,	// Read strobe width
  EMIF_CE2CTL1_MTYPE_32BIT_SDRAM,	// 32-bit-wide SDRAM
  EMIF_CE3CTL1_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE3CTL1_READ_HOLD_DEFAULT	// Read hold width
  ),
EMIF_CE3CTL2_RMK(					// CE3 Space Control Register 2
  EMIF_CE3CTL2_WRITE_SETUP_DEFAULT,	// Write setup width
  EMIF_CE3CTL2_WRITE_STROBE_DEFAULT,// Write strobe width
  EMIF_CE3CTL2_WRITE_HOLD_DEFAULT,	// Write hold width
  EMIF_CE3CTL2_READ_SETUP_DEFAULT	// Read setup width
  ),
EMIF_SDCTL1_RMK(					// SDRAM Control Register 1
  EMIF_SDCTL1_TRC_OF(6),			// Specifies tRC value of the SDRAM in EMIF clock cycles.
  EMIF_SDCTL1_SLFRFR_DISABLED		// Auto-refresh mode
  ),
EMIF_SDCTL2_RMK(					// SDRAM Control Register 2
  0x11,								// 4 banks,11 row address, 8 column address
  EMIF_SDCTL2_RFEN_ENABLED,			// Refresh enabled
  EMIF_SDCTL2_INIT_INIT_SDRAM,
  EMIF_SDCTL2_TRCD_OF(1),			// Specifies tRCD value of the SDRAM in EMIF clock cycles
  EMIF_SDCTL2_TRP_OF(1)				// Specifies tRP value of the SDRAM in EMIF clock cycles
  ),
0x61B,								// SDRAM Refresh Control Register 1
0x0300,								// SDRAM Refresh Control Register 2