399_init.h

st7710的tuner标准驱动

/* -------------------------------------------------------------------------
File Name: 399_init.h

Description: 399 register mappings.

Copyright (C) 1999-2001 STMicroelectronics

History:
   date: 10-October-2001
version: 1.0.0
 author: SA
comment: STAPIfied by GP

---------------------------------------------------------------------------- */


/* define to prevent recursive inclusion */
#ifndef H_399INIT
 #define H_399INIT


 /* common includes ---------------------------------------------------------------- */
#ifndef STTUNER_REG_INIT_OLD_METHOD /* this option will be removed later & only the new method will be left in file*/



/* ID */
 #define R399_ID 0x0
 #define F399_CHIP_IDENT 0xf0
 #define F399_RELEASE 0xf

/* I2CRPT */
 #define R399_I2CRPT 0x1
 #define F399_I2CT_ON 0x10080
 #define F399_ENARPT_LEVEL 0x10070
 #define F399_SCLT_DELAY 0x10008
 #define F399_SCLT_VALUE 0x10004
 #define F399_STOP_ENABLE 0x10002
 #define F399_SDAT_VALUE 0x10001

/* ACR */
 #define R399_ACR 0x2
 #define F399_PRESCALER 0x200e0
 #define F399_DIVIDER 0x2001f

/* F22FR */
 #define R399_F22FR 0x3
 #define F399_F_REG 0x300ff

/* DACR1 */
 #define R399_DACR1 0x4
 #define F399_DACMODE 0x400e0
 #define F399_DACR1_4 0x40010
 #define F399_DACMSB 0x4000f

/* DACR2 */
 #define R399_DACR2 0x5
 #define F399_DACLSB 0x500ff

/* DISEQC */
 #define R399_DISEQC 0x6
 #define F399_TIM_OFF 0x60080
 #define F399_DISEQC_6 0x60040
 #define F399_TIM_CMD 0x60030
 #define F399_CMD_ENV 0x60008
 #define F399_DISEQC 0x60004
 #define F399_DISEQCMODE 0x60003

/* DISEQCFIFO */
 #define R399_DISEQCFIFO 0x7
 #define F399_DISEQCFIFO1 0x700ff

/* DISEQCSTATUS */
 #define R399_DISEQCSTATUS 0x8
 #define F399_IP0 0x80080
 #define F399_ATT 0x80040
 #define F399_T5 0x80020
 #define F399_T4 0x80010
 #define F399_T3 0x80008
 #define F399_TIM 0x80004
 #define F399_FE 0x80002
 #define F399_FF 0x80001

/* DISEQC2 */
 #define R399_DISEQC2 0x9
 #define F399_DISEQC2_7 0x90080
 #define F399_DISEQC2_6 0x90040
 #define F399_DISEQC2_5 0x90020
 #define F399_DISEQC2_4 0x90010
 #define F399_DISEQC2_3 0x90008
 #define F399_DISEQC2_2 0x90004
 #define F399_DISEQC2_1 0x90002
 #define F399_DISEQC2_0 0x90001

/* IOCFG1 */
 #define R399_IOCFG1 0xa
 #define F399_LOCK_CONF 0xa00e0
 #define F399_LOCK_OPDRAIN 0xa0010
 #define F399_SERIAL_D0 0xa0008
 #define F399_TURBO_OUTMODE 0xa0007

/* IOCFG2 */
 #define R399_IOCFG2 0xb
 #define F399_OP1_OPDRAIN 0xb0080
 #define F399_OP1_1 0xb0040
 #define F399_OP0_OPDRAIN 0xb0020
 #define F399_OP0_1 0xb0010
 #define F399_DCHIP_ADDR 0xb000c
 #define F399_DIFF_MODE 0xb0002
 #define F399_OUTRS_HZ 0xb0001

/* AGC0C */
 #define R399_AGC0C 0xc
 #define F399_PROG0 0xc00f8
 #define F399_BETA0 0xc0007

/* AGC0R */
 #define R399_AGC0R 0xd
 #define F399_REF_AGC0 0xd00fc
 #define F399_LUT_ORD 0xd0002
 #define F399_DC0_ADJ 0xd0001

/* AGC1C */
 #define R399_AGC1C 0xe
 #define F399_DC1_ADJ 0xe0080
 #define F399_DBLE_AGC 0xe0040
 #define F399_AGC1_B2_EN 0xe0020
 #define F399_BETA2 0xe0018
 #define F399_AGC1C_BETA1 0xe0007

/* AGC1CN */
 #define R399_AGC1CN 0xf
 #define F399_AVERAGE_ON 0xf0080
 #define F399_SEL_AVERAGE_ADJ 0xf0040
 #define F399_AGC2GAIN 0xf0030
 #define F399_SEL_ADCOUT 0xf0008

/* RTC */
 #define R399_RTC 0x10
 #define F399_RTC_7 0x100080
 #define F399_ALPHA_TMG 0x100070
 #define F399_RTC_3 0x100008
 #define F399_BETA_TMG 0x100007

/* AGC1R */
 #define R399_AGC1R 0x11
 #define F399_IAGC1R 0x110080
 #define F399_AGC_BEF_DC 0x110040
 #define F399_AGC1R_REF 0x11003f

/* AGC1RN */
 #define R399_AGC1RN 0x12
 #define F399_IAGC1RN 0x120080
 #define F399_OPEN_DRAIN 0x120040
 #define F399_AGC1RN_REF 0x12003f

/* AGC2O */
 #define R399_AGC2O 0x13
 #define F399_AGC2COEFF 0x1300e0
 #define F399_AGC2_REF 0x13001f

/* TLSR */
 #define R399_TLSR 0x14
 #define F399_STEP_MINUS 0x1400f0
 #define F399_STEP_PLUS 0x14000f

/* CFD */
 #define R399_CFD 0x15
 #define F399_CFD_ON 0x150080
 #define F399_BETA_FC 0x150070
 #define F399_FDCT 0x15000c
 #define F399_LDL 0x150003

/* ACLC */
 #define R399_ACLC 0x16
 #define F399_DEROT_ON_OFF 0x160080
 #define F399_ACLC 0x160040
 #define F399_NOISE 0x160030
 #define F399_ALPHA 0x16000f

/* BCLC */
 #define R399_BCLC 0x17
 #define F399_ALGO 0x1700c0
 #define F399_BETA 0x17003f

/* R8PSK */
 #define R399_R8PSK 0x18
 #define F399_MODE_8PSK 0x180080
 #define F399_EGAL_ON 0x180040
 #define F399_OUT_IQ_8PSK 0x180020
 #define F399_R8PSK_4 0x180010
 #define F399_MODE_COEF 0x180008
 #define F399_MU_8PSK 0x180007

/* LDT */
 #define R399_LDT 0x19
 #define F399_LOCK_THRESHOLD 0x1901ff

/* LDT2 */
 #define R399_LDT2 0x1a
 #define F399_LOCK_THRESHOLD2 0x1a01ff

/* AGC0CMD */
 #define R399_AGC0CMD 0x1b
 #define F399_LOCK0_CMD 0x1b00c0
 #define F399_LOCK0_INFO 0x1b0020
 #define F399_AUTO_SPLIT 0x1b0010
 #define F399_AMPLI6DB 0x1b0008
 #define F399_AGC0CMD_2 0x1b0004
 #define F399_AGC0CMD_1 0x1b0002
 #define F399_AGC0CMD_0 0x1b0001

/* AGC0I */
 #define R399_AGC0I 0x1c
 #define F399_AGC0I_7 0x1c0080
 #define F399_AGC0I_6 0x1c0040
 #define F399_AGC0I_5 0x1c0020
 #define F399_AGC0I_4 0x1c0010
 #define F399_AGC0_INT 0x1c000f

/* AGC1S */
 #define R399_AGC1S 0x1d
 #define F399_AGC1_INT_SEC 0x1d01ff

/* AGC1P */
 #define R399_AGC1P 0x1e
 #define F399_AGC1_INT_PRIM 0x1e01ff

/* AGC1IN */
 #define R399_AGC1IN 0x1f
 #define F399_AGC1_VALUE 0x1f00ff

/* TLIR */
 #define R399_TLIR 0x20
 #define F399_TMG_LOCK_IND 0x2000ff

/* AGC2I1 */
 #define R399_AGC2I1 0x21
 #define F399_AGC2_INTEGRATOR_MSB 0x2100ff

/* AGC2I2 */
 #define R399_AGC2I2 0x22
 #define F399_AGC2_INTEGRATOR_LSB 0x2200ff

/* RTF */
 #define R399_RTF 0x23
 #define F399_TIMING_LOOP_FREQ 0x2301ff

/* VSTATUS */
 #define R399_VSTATUS 0x24
 #define F399_CF 0x240080
 #define F399_VSTATUS_6 0x240040
 #define F399_VSTATUS_5 0x240020
 #define F399_PRF 0x240010
 #define F399_LK 0x240008
 #define F399_PR 0x240007

/* LDI */
 #define R399_LDI 0x25
 #define F399_LOCK_DET_INTEGR 0x2501ff

/* ECNTM */
 #define R399_ECNTM 0x26
 #define F399_ERROR_COUNT_MSB 0x2600ff

/* ECNTL */
 #define R399_ECNTL 0x27
 #define F399_ERROR_COUNT_LSB 0x2700ff

/* SFRH */
 #define R399_SFRH 0x28
 #define F399_SYMB_FREQ_HSB 0x2800ff

/* SFRM */
 #define R399_SFRM 0x29
 #define F399_SYMB_FREQ_MSB 0x2900ff

/* SFRL */
 #define R399_SFRL 0x2a
 #define F399_SYMB_FREQ_LSB 0x2a00f0

/* CFRM */
 #define R399_CFRM 0x2b
 #define F399_CARRIER_FREQUENCY_MSB 0x2b00ff

/* CFRL */
 #define R399_CFRL 0x2c
 #define F399_CARRIER_FREQUENCY_LSB 0x2c00ff

/* NIRM */
 #define R399_NIRM 0x2d
 #define F399_NOISE_IND_MSB 0x2d00ff

/* NIRL */
 #define R399_NIRL 0x2e
 #define F399_NOISE_IND_LSB 0x2e00ff

/* VERROR */
 #define R399_VERROR 0x2f
 #define F399_ERROR_VAL 0x2f00ff

/* FECM */
 #define R399_FECM 0x30
 #define F399_FECMODE 0x3000f0
 #define F399_FECM3 0x300008
 #define F399_VIT_DIFF 0x300004
 #define F399_SYNC 0x300002
 #define F399_SYM 0x300001

/* VTH0 */
 #define R399_VTH0 0x31
 #define F399_VTH0 0x31007f

/* VTH1 */
 #define R399_VTH1 0x32
 #define F399_VTH1 0x32007f

/* VTH2 */
 #define R399_VTH2 0x33
 #define F399_VTH2 0x33007f

/* VTH3 */
 #define R399_VTH3 0x34
 #define F399_VTH3 0x34007f

/* VTH4 */
 #define R399_VTH4 0x35
 #define F399_VTH4 0x35007f

/* VTH5 */
 #define R399_VTH5 0x36
 #define F399_VTH5 0x36007f

/* PR */
 #define R399_PR 0x37
 #define F399_E7 0x370080
 #define F399_E6 0x370040
 #define F399_PR_7_8 0x370020
 #define F399_PR_6_7 0x370010
 #define F399_PR_5_6 0x370008
 #define F399_PR_3_4 0x370004
 #define F399_PR_2_3 0x370002
 #define F399_PR_1_2 0x370001

/* VAVSRCH */
 #define R399_VAVSRCH 0x38
 #define F399_AM 0x380080
 #define F399_F 0x380040
 #define F399_SN 0x380030
 #define F399_TO 0x38000c
 #define F399_H 0x380003

/* RS */
 #define R399_RS 0x39
 #define F399_DEINT 0x390080
 #define F399_OUTRS_PS 0x390040
 #define F399_RS 0x390020
 #define F399_DESCRAM 0x390010
 #define F399_ERR_BIT 0x390008
 #define F399_MPEG 0x390004
 #define F399_CLK_POL 0x390002
 #define F399_CLK_CFG 0x390001

/* RSOUT */
 #define R399_RSOUT 0x3a
 #define F399_INV_DVALID 0x3a0080
 #define F399_INV_DSTART 0x3a0040
 #define F399_INV_DERROR 0x3a0020
 #define F399_EN_STBACKEND 0x3a0010
 #define F399_ENA8_LEVEL 0x3a000f

/* ERRCTRL */
 #define R399_ERRCTRL 0x3b
 #define F399_ERRMODE 0x3b0080