rf4kcclib.c

st7710的tuner标准驱动

/ In the case of failures 2 and 3, the frequency of failure is encoded
/ in bits 0 thru 4.  This return value represents the last failure that
/ occurred.  There may be other failures.  See the operational note below.
/ 	OPERATIONAL NOTE: The array "f0ctrlFreqs" is an array of structures where
/ the 1st is the frequency, and the 2nd is a default value of f0ctrl 
/ The 3rd value represents the actual f0ctrl found during this routine.
/ In the case of a type 2 or 3 failure, this default is placed in the
/ "actual" location so that the chip may continue to operate, although not
/ necessarily at the optimum level.*/
ST_ErrorCode_t powerUpSequence(STTUNER_IOREG_DeviceMap_t *DeviceMap, IOARCH_Handle_t IOHandle,S32 fxtal, S32 stepSize, 
											S32 crystalOut, S32 crystalOsc)
{
	S32 j;
	ST_ErrorCode_t Error = ST_NO_ERROR;
	
	for (j=0; j<NBR_F0CTRL; j++)
	{
		f0ctrlFreqs[j].act_f0ctrl = f0ctrlFreqs[j].def_f0ctrl;
	}

	
	Error = chipOn(DeviceMap,IOHandle);

	
	if (Error != ST_NO_ERROR )
	{
		return Error;
	}

	for (j = (NBR_F0CTRL - 1); j >= 0; j--) 
	{
		
		Error = setLO1(DeviceMap,IOHandle, f0ctrlFreqs[j].freq, fxtal, stepSize);

		
		if (Error != ST_NO_ERROR)
		{			
			continue;
		}
		
		
		Error  = setLNACal(DeviceMap,IOHandle, f0ctrlFreqs[j].freq);
		
		
		if (Error != ST_NO_ERROR)
		{			
			Error = setLNACal(DeviceMap,IOHandle, f0ctrlFreqs[j].freq);
		}
		if (Error != ST_NO_ERROR)
		{
			 Error = setLNACal(DeviceMap,IOHandle, f0ctrlFreqs[j].freq);
		}
		if (Error != ST_NO_ERROR)
		{       
			Error = setLNACal(DeviceMap,IOHandle, f0ctrlFreqs[j].freq);
		}
		if (Error != ST_NO_ERROR)
		{
			Error  = setLNACal(DeviceMap,IOHandle, f0ctrlFreqs[j].freq);
		}					   

		
		if (Error != ST_NO_ERROR)
		{
			continue;
		}

		
		f0ctrlFreqs[j].act_f0ctrl = tmpF0ctrl;
	}

	
	return Error;
}


/* this function performs a full channel change.  It utilizes other, but required library
/functions to make the change.  In addition, it performs a "short cut" technique for the
/ LNA Cal sequence: a f0ctrl table look-up, and direct write to the registers of the value.
/ The return value is zero for "OK", and an integer "1" to indicate a no lock condition on
/ the LO1 VCO.  If there is an error in finding the frequency value in the table, then
/ the return value is "2".  If the requested channel frequency is out of range, then
/ the return value is "3".  If there is a Two Wire Bus error, the return is 4.*/
ST_ErrorCode_t setChannel(STTUNER_IOREG_DeviceMap_t *DeviceMap, IOARCH_Handle_t IOHandle, U32 fchan, S32 fxtal, S32 stepSize)
{
	S32 j			= 0;
	S32 retVal		= 1;	/* Initially set for an error return.*/
	S32 band		= 2;	/* Indicates mid or high band, initially set to mid band.*/
	S32 minF0ctrl	= 0;
	S32 maxF0ctrl	= 0;
	U32 tmpInt		= 0;
	U32	minFreq		= 0;
	U32	maxFreq		= 0;
	U8	fctrl		= 0;
	U8	lcpl		= 0;
	U8	lcfc		= 0;
	U8	dqcw		= 0;
	U8	lds1		= 0;
	U8	lnen		= 0;
	U8	lds2		= 0;
        ST_ErrorCode_t Error = ST_NO_ERROR;
	
	if ((fchan < (U32)MIN_CHANNEL) || (fchan > (U32)MAX_CHANNEL))
	{
		return ST_ERROR_BAD_PARAMETER;
	}

	
	Error = setLO1(DeviceMap,IOHandle, fchan, fxtal, stepSize);

	
	if (Error != ST_NO_ERROR)
	{
		
		return Error;
	}

	
	retVal = 2;

	
	for (j = 0; j < TABLELNACS_LEN; j++)
	{
		if ( (tableLNACS[j].chanMin <= fchan) && (fchan < tableLNACS[j].chanMax) )
		{
			lcpl = tableLNACS[j].lcpl;
			lcfc = tableLNACS[j].lcfc;
			dqcw = tableLNACS[j].dqcw;
			lds1 = tableLNACS[j].lds1;
			lnen = tableLNACS[j].lnen;
			lds2 = tableLNACS[j].lds2;
			band = tableLNACS[j].lnen;
			break;
		}
	}

	
	if (fchan > MAX_FREQ)
	{
		
		fchan = MAX_FREQ;
		dqcw = (U8)DEQ_CTRL_VAL;
	}

	
	if (band == MID_BAND)
	{
		
		for (j=0; j < (NBR_MIDBAND - 1); j++)
		{
			if ( (f0ctrlFreqs[j].freq <= fchan) && (fchan <= f0ctrlFreqs[j + 1].freq) )
			{
				
				maxF0ctrl = f0ctrlFreqs[j].act_f0ctrl * 10;
				minF0ctrl = f0ctrlFreqs[j + 1].act_f0ctrl * 10;
				minFreq = f0ctrlFreqs[j].freq;
				maxFreq = f0ctrlFreqs[j + 1].freq;
				retVal = 0;	
				break;
			}
		}
	}
	else
	{
		
		for (j=(NBR_MIDBAND); j < (NBR_F0CTRL - 1); j++)
		{
			if ( (f0ctrlFreqs[j].freq <= fchan) && (fchan <= f0ctrlFreqs[j + 1].freq) )
			{
				
				maxF0ctrl = f0ctrlFreqs[j].act_f0ctrl * 10;
				minF0ctrl = f0ctrlFreqs[j + 1].act_f0ctrl * 10;
				minFreq = f0ctrlFreqs[j].freq;
				maxFreq = f0ctrlFreqs[j + 1].freq;
				retVal = 0;	
				break;
			}
		}
	}

	
	if (retVal > 0)
	{
		
		return retVal;
	}

	
	tmpInt = ((fchan - minFreq) / ((maxFreq - minFreq) / 100));
	fctrl = (U8)((maxF0ctrl - ((tmpInt * (maxF0ctrl - minF0ctrl)) / 100) + 5) / 10);

	Error   = (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_LCPL, (S32)LCPL_DWN);
	Error  |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_LCFC, (S32)fctrl);
	Error  |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_DQCW, (S32)dqcw);
	Error  |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_LCFR, (S32)LCFR_WSW);
	Error  |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_LDS1, (S32)lds1);
	Error  |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_LNEN, (S32)lnen);
	Error  |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_LDS2, (S32)lds2);

	if (Error != ST_NO_ERROR)
	{
		return Error;
	}

	
	return 0;
}



U32 getChannelFreq(STTUNER_IOREG_DeviceMap_t *DeviceMap,IOARCH_Handle_t IOHandle)
{
	S32	B		= 0;
	S32	A		= 0;
	S32	R		= 0;
	U32	tmpInt	= 0;
	U32	fcmp	= 0;
	U32	lodv	= 0;
		
	
	R = STTUNER_IOREG_GetField(DeviceMap,IOHandle,FRF4000_R);/*previously getfieldval*/

	switch(R)
	{
		case 24:				/* crystal = 24 MHz.*/
		case 22:				/* crystal = 22 MHz.*/
		default:				/* Just in case...*/
			fcmp = 1000000;
			break;

		case 36:				/*crystal = 24 MHz.*/
		case 33:				/* crystal = 22 MHz.*/
			fcmp = 666667;
			break;

		case 48:				/*crystal = 24 MHz.*/
		case 44:				/* crystal = 22 MHz*/
			fcmp = 500000;
			break;
	}

	  	
	
	B = STTUNER_IOREG_GetField(DeviceMap,IOHandle,FRF4000_B);/*previously getfieldval*/
		
	
	A = STTUNER_IOREG_GetField(DeviceMap,IOHandle,FRF4000_A);/*previously getfieldval*/
	
	
	tmpInt =STTUNER_IOREG_GetField(DeviceMap,IOHandle,FRF4000_LODV);/*previously getfieldval*/
	switch(tmpInt)
	{
		case 0:
		case 1:
		case 4:
		case 5:
			lodv = 4;
			break;

		case 3:
			lodv = 8;
			break;

		case 2:
			lodv = 16;
			break;
		
		case 6:
			lodv = 32;
			break;

		case 7:
		default:
			lodv = 64;
			break;
	}
	
	if ((fcmp == 1000000) || (fcmp == 500000))
	{
		return (fcmp / lodv) * ((32 * B) + A);
	}
	else
	{
		
		fcmp = (((fcmp * 10) / lodv) + 5) / 10;
		return fcmp * ((32 * B) + A);
	}
}



ST_ErrorCode_t doOneTimeDecComp(STTUNER_IOREG_DeviceMap_t *DeviceMap, IOARCH_Handle_t IOHandle)
{
	U8 reg	= 0;
         ST_ErrorCode_t Error = ST_NO_ERROR;
	
	if ( STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCFP, 0) != ST_NO_ERROR)
	{
		
		return Error;
	}

	
	if (STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCSC, 1) != ST_NO_ERROR)
	{
		
		return Error;
	}

	
	if (reg == 0)
	{
		
		reg = 1;
	}
	else
	{
		reg = 0;
	}

	
	if (STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCFP, reg) != ST_NO_ERROR)
	{
		
		return Error;
	}
	
	if (STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCSC, 0) != ST_NO_ERROR)
	{
		
		return Error;
	}
	
	return Error;
}


S32 getF0ctrlValue(S32 offset, S32* freqVal)
{
	S32 retVal = 0;
	
	
	if ((offset < 0) || (offset >= (S32)NBR_F0CTRL))
	{
		
		retVal = 1;
	}
	else
	{
		
		*freqVal = (U32)f0ctrlFreqs[offset].act_f0ctrl;
	}
	
	return retVal;
}


/* This is the initialization function.  It defines and sets all
 the chips registers.  It must be called after "open".
 The argument crystalOut, and crystalOsc set the initial state of the
 crystal output buffer and the crystal oscillator, respectively.  For either
 argument, a value of 0 sets the condition to on, and a value of 1 sets the
 condition to off.
 Zero is returned for success, and a "1" is returned for a "no lock" error
 condition on LO2.  */
ST_ErrorCode_t RF4000_doInit(TUNTDRV_InstanceData_t *Instance)
{
	U8	tmpU8	= 0;
	U32	stepSize = 0;	
	U8 *DefVal;
	ST_ErrorCode_t Error= ST_NO_ERROR;
	stepSize = Instance->StepSize;
	DefVal = DefRF4000Val;
	
	
 	
	tmpU8 = (U8)STTUNER_IOREG_RegGetDefaultVal(&(Instance->DeviceMap),DefRF4000Val,RF4000_Address,RF4000_NBREGS,RRF4000_REGISTER49);
	
	
	tmpU8 &= (U8)XRGN_CLR;
	tmpU8 &= (U8)XOBN_CLR;
	
	
	if ((U32)RF4000_CRYSTALBUF == 0)
	{
		
		tmpU8 |= (U8)XOBN_ENA << (S32)XOBN_BIT;
	}
	else
	{
		
		tmpU8 |= (U8)XOBN_DIS << (S32)XOBN_BIT;
	}

	
	if ((U32)RF4000_CRYSTALOSC == 0)
	{
		
		tmpU8 |= (U8)XRGN_ENA << (S32)XRGN_BIT;
	}
	else
	{
		
		tmpU8 |= (U8)XRGN_DIS << (S32)XRGN_BIT;
	}

	
	STTUNER_IOREG_RegSetDefaultVal(&(Instance->DeviceMap),DefRF4000Val,RF4000_Address,RF4000_NBREGS,RRF4000_REGISTER49, tmpU8);
	
	
	
	
	if ( powerUpSequence(&(Instance->DeviceMap), Instance->IOHandle,RF4000_FXTAL, stepSize,
								RF4000_CRYSTALBUF, RF4000_CRYSTALOSC)!= ST_NO_ERROR)
	{
		return Error;
	}

	
	if ( baseBandFltrCal(&(Instance->DeviceMap), Instance->IOHandle, Instance->ChannelBW, RF4000_THERM_ON) != ST_NO_ERROR)
	{
		return Error;
	}
	

	
	return 0;
}