📄 rf4kcclib.c
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else if (stepSize == 666667)
{
Np = Fvco / 666667;
R = 36;
}
else
{
Np = Fvco / 500000;
R = 48;
}
}
else
{
if (stepSize == 1000000)
{
Np = Fvco / 1000000;
R = 22;
}
else if (stepSize == 666667)
{
Np = Fvco / 666667;
R = 33;
}
else
{
Np = Fvco / 500000;
R = 44;
}
}
/* Determine the value of cprs based on the NRVSNC table.
A default value of 0 will be used if there
is no match found in the table. First, check for a match
to the maximum value.*/
if ( Np == tableNRVSNC[tableNRVSNC_LEN - 1].maxN )
{
/* Extract the value and shift it to the correct bit.*/
cprs = tableNRVSNC[tableNRVSNC_LEN - 1].cprs;
}
else
{
for (j = 0; j < tableNRVSNC_LEN; j++)
{
if ( (tableNRVSNC[j].minN <= Np) && (Np < tableNRVSNC[j].maxN) )
{
/*Extract the value and shift it to the correct bit.*/
cprs = tableNRVSNC[j].cprs;
break;
}
}
}
B = (U8)(Np / 32);
A = (U8)(Np % 32);
Error = (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_OSCS, (S32)oscs);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_CPRS, (S32)cprs);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_FBPS, (S32)fbps);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LODV, (S32)lodv);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCDS, (S32)lcds);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_B, (S32)B);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_A, (S32)A);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_R, (S32)R);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_OKS1, (S32)OKS1_DIV);
Error |= STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_VSS1, 1);
rf4kDelay(1);
/* Set the trigger bit back to 0.*/
Error |= STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_VSS1, 0) ;
/*Now, poll register DLCK1, for 80 ms, or until
/ the value = 1, which indicates a VCO lock. Report an
/ error if a lock doesn't occur.
/ Changed from analog to digital lock: 8/3/05.*/
for (j = 0; j < 80; j++)
{
temp = (U8)STTUNER_IOREG_GetField(DeviceMap, IOHandle, FRF4000_DLCK1);
if (temp == 1)
{
/* Got a lock, so exit the loop.*/
break;
}
else
rf4kDelay(1);
}
/* Check for a "no lock" condition on LO1. If
/ found, then set the appropriate error code
/ for the return.*/
if (j >= 80)
{
Error = FE_RF4K_TERM_TIMEOUT;
}
rf4kDelay(13);
Error |= STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_OKS1, OKS1_OFF) ;
return Error;
}
ST_ErrorCode_t setLNACal(STTUNER_IOREG_DeviceMap_t *DeviceMap, IOARCH_Handle_t IOHandle, U32 fchan)
{
S32 j;
S32 retVal = 0; /* Initially set for an "OK" return.*/
S32 f0ctrl = 0;
U8 lcpl = 0;
U8 lcfc = 0;
U8 dqcw = 0;
U8 lds1 = 0;
U8 lnen = 0;
U8 lds2 = 0;
U8 tmpUChar;
U8 varBCOR;
U8 varVGAS;
U8 varVGAG;
U8 varBCON;
U8 varBDBW;
U8 varLAEN;
U8 varLAHO;
ST_ErrorCode_t Error = ST_NO_ERROR;
doOneTimeDecComp(DeviceMap,IOHandle);
varBCOR = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_BCOR);
varVGAS = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_VGAS);
varVGAG = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_VGAG);
varBCON = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_BCON);
varBDBW = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_BDBW);
varLAEN = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_LAEN);
varLAHO = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_LAHO);
Error = (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_BCOR, (S32)BCOR_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_VGAS, (S32)VGAS_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_VGAG, (S32)VGAG_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_BCON, (S32)BCON_OVR);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_BDBW, (S32)BDBW_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCTW, (S32)LCTW_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCTN, (S32)LCTN_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCGN, (S32)LCGN_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCAW, (S32)LCAW_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LAEN, (S32)LAEN_VAL);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LAHO, (S32)LAHO_VAL);
if (Error != ST_NO_ERROR )
{
return Error;
}
for (j = 0; j < TABLELNACS_LEN; j++)
{
if ( (tableLNACS[j].chanMin <= fchan) && (fchan < tableLNACS[j].chanMax) )
{
lcpl = tableLNACS[j].lcpl;
lcfc = tableLNACS[j].lcfc;
dqcw = tableLNACS[j].dqcw;
lds1 = tableLNACS[j].lds1;
lnen = tableLNACS[j].lnen;
lds2 = tableLNACS[j].lds2;
break;
}
}
Error = (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCPL, (S32)lcpl);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCFC, (S32)lcfc);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_DQCW, (S32)dqcw);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LDS1, (S32)lds1);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LNEN, (S32)lnen);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LDS2, (S32)lds2);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCFR, (S32)LCFR_WSM);
if (Error != ST_NO_ERROR)
{
return Error;
}
if ( STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCAL, 1) != ST_NO_ERROR)
{
return Error;
}
rf4kDelay(1);
if ( STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LCAL, 0) != ST_NO_ERROR)
{
return Error;
}
for (j = 0; j < 100; j++)
{
tmpUChar = (U8)STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_LCOM);
if (tmpUChar > 0)
{
break;
}
else
rf4kDelay(1);
}
f0ctrl = STTUNER_IOREG_GetField(DeviceMap,IOHandle, FRF4000_LCFCR);
tmpF0ctrl = (U8)f0ctrl;
retVal = (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_BCOR, (S32)varBCOR);
retVal += (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_VGAS, (S32)varVGAS);
retVal += (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_VGAG, (S32)varVGAG);
retVal += (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_BCON, (S32)varBCON);
retVal += (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_BDBW, (S32)varBDBW);
retVal += (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LAEN, (S32)varLAEN);
retVal += (S32)STTUNER_IOREG_SetField(DeviceMap,IOHandle, FRF4000_LAHO, (S32)varLAHO);
if (Error != ST_NO_ERROR)
{
return Error;
}
if ( (j < 100) && (tmpUChar == (U8)3) )
{
Error = ST_NO_ERROR;
}
else
{
if (tmpUChar == (U8)2)
{
retVal = 2;
}
else if (tmpUChar == (U8)1)
{
retVal = 1;
}
else
{
retVal = 3;
}
}
return Error;
}
ST_ErrorCode_t baseBandFltrCal(STTUNER_IOREG_DeviceMap_t *DeviceMap, IOARCH_Handle_t IOHandle, S32 filterBW, S32 thermalMode)
{
S32 j;
S32 retVal = 0; /* Initially set for an "OK" return.*/
S32 xtalFreq = 0; /* Zero equals 22 MHz, 1 equals 24 MHz.*/
U8 rcmd = 0;
U8 rcsp = 0;
U8 tmpUChar;
ST_ErrorCode_t Error = ST_NO_ERROR;
/* Determine the operating crystal/IF frequency. Get this from
/ the default register.*/
xtalFreq = (S32)(((U8)STTUNER_IOREG_RegGetDefaultVal(DeviceMap,DefRF4000Val,RF4000_Address,RF4000_NBREGS,RRF4000_REGISTER19) & ~(U8)RCXS_CLR) >> (S32)RCXS_BIT);
Error = (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle,FRF4000_BCON, (S32)BCON_STM);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCTN, (S32)RCTN_DIS);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCRN, (S32)RCRN_DIS);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCOT, (S32)RCOT_DIS);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCTM, (S32)RCTM_DIS);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCON, (S32)RCON_DIS);
if (retVal != ST_NO_ERROR)
{
return Error;
}
for (j = 0; j < TABLEWVCCFR_LEN; j++)
{
if (xtalFreq == 1)
{
if (filterBW == tableWVCCFR_24[j].bw)
{
rcmd = tableWVCCFR_24[j].rcmd;
rcsp = tableWVCCFR_24[j].rcsp;
break;
}
}
else
{
if (filterBW == tableWVCCFR_22[j].bw)
{
rcmd = tableWVCCFR_22[j].rcmd;
rcsp = tableWVCCFR_22[j].rcsp;
break;
}
}
}
Error = (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCMD, (S32)rcmd);
Error |= (S32)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCSP, (S32)rcsp);
if (retVal != ST_NO_ERROR)
{
return Error;
}
if ( STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCOT, 1) != ST_NO_ERROR)
{
return Error;
}
rf4kDelay(1);
if ( STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCOT, 0) != ST_NO_ERROR)
{
return Error;
}
for (j = 0; j < 100; j++)
{
tmpUChar = (U8)STTUNER_IOREG_GetField(DeviceMap, IOHandle, FRF4000_RCCND);
if ( tmpUChar )
{
rf4kDelay(1);
}
else
{
break;
}
}
if (j >= 100)
{
retVal = 1;
}
tmpUChar = (U8)STTUNER_IOREG_GetField(DeviceMap, IOHandle, FRF4000_RCCAL);
if ( STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_BCOR, tmpUChar) != ST_NO_ERROR)
{
return Error;
}
if (thermalMode == 1)
{
Error = (U8)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCTN, 1);
Error += (U8)STTUNER_IOREG_SetField(DeviceMap, IOHandle, FRF4000_RCTM, 1);
if (Error != ST_NO_ERROR)
{
return Error;
}
}
return Error;
}
/* This function is used to power-up the chip. It calls the "chip on"
/ sequence, but differs since it creates a table of f0ctrl values by
/ repeatedly setting LO1 and doing an LNA Cal for a list of frequencies.
/ A return value of 0 indicates a successful result. Return values
/ greater than 0 indicate an error, where the error type is encoded
/ in the return value as follows: the 1st 5 bits <4:0> contain an offset
/ into the "f0ctrlFreqs" array, which will provide the frequency at which
/ the failure took place. The last 2 bits <7:6> contain the error type,
/ where 1 = LO2 lock failure during chip on: 2 = LO1 lock failure at
/ one of the frequencies in the "f0ctrlFreqs" array: 3 = LNA Cal failure
/ at one of the frequencies in the "f0ctrlFreqs" array: 4 = not assigned.
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