d0362_map.h

st7710的tuner标准驱动

 #define F0362_COM_AGC_TARGET_LSB 0x007200f0
 #define F0362_COM_ENMODE 0x0072000f

/*	COM_AGC_CFG	*/
 #define R0362_COM_AGC_CFG 0x0073
 #define F0362_COM_N 0x007300f8
 #define F0362_COM_STABMODE 0x00730006
 #define F0362_ERR_SEL 0x00730001

/*	COM_AGC_GAIN1	*/
 #define R0362_COM_AGC_GAIN1 0x0074
 #define F0362_COM_GAIN1ACK 0x007400f0
 #define F0362_COM_GAIN1TRK 0x0074000f

/*	AUT_AGC_TARGET_MSB	*/
 #define R0362_AUT_AGC_TARGET_MSB 0x0075
 #define F0362_AUT_AGC_TARGET_MSB 0x007500ff

/*	LOCK_DETECT_MSB	*/
 #define R0362_LOCK_DETECT_MSB 0x0076
 #define F0362_LOCK_DETECT_MSB 0x007600ff

/*	AGCTAR_LOCK_LSBS	*/
 #define R0362_AGCTAR_LOCK_LSBS 0x0077
 #define F0362_AUT_AGC_TARGET_LSB 0x007700f0
 #define F0362_LOCK_DETECT_LSB 0x0077000f

/*	AUT_GAIN_EN	*/
 #define R0362_AUT_GAIN_EN 0x0078
 #define F0362_AUT_ENMODE 0x007800f0
 #define F0362_AUT_GAIN2 0x0078000f

/*	AUT_CFG	*/
 #define R0362_AUT_CFG 0x0079
 #define F0362_AUT_N 0x007900f8
 #define F0362_INT_CHOICE 0x00790006
 #define F0362_INT_LOAD 0x00790001

/*	LOCKN	*/
 #define R0362_LOCKN 0x007a
 #define F0362_LOCKN 0x007a00f8
 #define F0362_SEL_IQNTAR 0x007a0004
 #define F0362_LOCK_DETECT_CHOICE 0x007a0003

/*	INT_X_3	*/
 #define R0362_INT_X_3 0x007b
 #define F0362_INT_X3 0x007b00ff

/*	INT_X_2	*/
 #define R0362_INT_X_2 0x007c
 #define F0362_INT_X2 0x007c00ff

/*	INT_X_1	*/
 #define R0362_INT_X_1 0x007d
 #define F0362_INT_X1 0x007d00ff

/*	INT_X_0	*/
 #define R0362_INT_X_0 0x007e
 #define F0362_INT_X0 0x007e00ff

/*	MIN_ERR_X_MSB	*/
 #define R0362_MIN_ERR_X_MSB 0x007f
 #define F0362_MIN_ERR_X_MSB 0x007f00ff

/*	STATUS_ERR_DA	*/
 #define R0362_STATUS_ERR_DA 0x006f
 #define F0362_COM_USEGAINTRK 0x006f0080
 #define F0362_COM_AGCLOCK 0x006f0040
 #define F0362_AUT_AGCLOCK 0x006f0020
 #define F0362_MIN_ERR_X_LSB 0x006f000f

/*	COR_CTL	*/
 #define R0362_COR_CTL 0x0080
 #define F0362_CORE_ACTIVE 0x00800020
 #define F0362_HOLD 0x00800010
 #define F0362_CORE_STATE_CTL 0x0080000f

/*	COR_STAT	*/
 #define R0362_COR_STAT 0x0081
 #define F0362_SCATT_LOCKED 0x00810080
 #define F0362_TPS_LOCKED 0x00810040
 #define F0362_SYR_LOCKED_COR 0x00810020
 #define F0362_AGC_LOCKED_STAT 0x00810010
 #define F0362_CORE_STATE_STAT 0x0081000f

/*	COR_INTEN	*/
 #define R0362_COR_INTEN 0x0082
 #define F0362_INTEN 0x00820080
 #define F0362_INTEN_SYR 0x00820020
 #define F0362_INTEN_FFT 0x00820010
 #define F0362_INTEN_AGC 0x00820008
 #define F0362_INTEN_TPS1 0x00820004
 #define F0362_INTEN_TPS2 0x00820002
 #define F0362_INTEN_TPS3 0x00820001

/*	COR_INTSTAT	*/
 #define R0362_COR_INTSTAT 0x0083
 #define F0362_INTSTAT_SYR 0x00830020
 #define F0362_INTSTAT_FFT 0x00830010
 #define F0362_INTSAT_AGC 0x00830008
 #define F0362_INTSTAT_TPS1 0x00830004
 #define F0362_INTSTAT_TPS2 0x00830002
 #define F0362_INTSTAT_TPS3 0x00830001

/*	COR_MODEGUARD	*/
 #define R0362_COR_MODEGUARD 0x0084
 #define F0362_FORCE 0x00840010
 #define F0362_MODE 0x0084000c
 #define F0362_GUARD 0x00840003

/*	AGC_CTL	*/
 #define R0362_AGC_CTL 0x0085
 #define F0362_AGC_TIMING_FACTOR 0x008500e0
 #define F0362_AGC_LAST 0x00850010
 #define F0362_AGC_GAIN 0x0085000c
 #define F0362_AGC_NEG 0x00850002
 #define F0362_AGC_SET 0x00850001

/*	AGC_MANUAL1	*/
 #define R0362_AGC_MANUAL1 0x0086
 #define F0362_AGC_VAL_LO 0x008600ff

/*	AGC_MANUAL2	*/
 #define R0362_AGC_MANUAL2 0x0087
 #define F0362_AGC_VAL_HI 0x0087000f

/*	AGC_TARGET	*/
 #define R0362_AGC_TARGET 0x0088
 #define F0362_AGC_TARGET 0x008800ff

/*	AGC_GAIN1	*/
 #define R0362_AGC_GAIN1 0x0089
 #define F0362_AGC_GAIN_LO 0x008900ff

/*	AGC_GAIN2	*/
 #define R0362_AGC_GAIN2 0x008a
 #define F0362_AGC_LOCKED_GAIN2 0x008a0010
 #define F0362_AGC_GAIN_HI 0x008a000f

/*	RESERVED_1	*/
 #define R0362_RESERVED_1 0x008b
 #define F0362_RESERVED_1 0x008b00ff

/*	RESERVED_2	*/
 #define R0362_RESERVED_2 0x008c
 #define F0362_RESERVED_2 0x008c00ff

/*	RESERVED_3	*/
 #define R0362_RESERVED_3 0x008d
 #define F0362_RESERVED_3 0x008d00ff

/*	CAS_CTL	*/
 #define R0362_CAS_CTL 0x008e
 #define F0362_CCS_ENABLE 0x008e0080
 #define F0362_ACS_DISABLE 0x008e0040
 #define F0362_DAGC_DIS 0x008e0020
 #define F0362_DAGC_GAIN 0x008e0018
 #define F0362_CCSMU 0x008e0007

/*	CAS_FREQ	*/
 #define R0362_CAS_FREQ 0x008f
 #define F0362_CCS_FREQ 0x008f00ff

/*	CAS_DAGCGAIN	*/
 #define R0362_CAS_DAGCGAIN 0x0090
 #define F0362_CAS_DAGC_GAIN 0x009000ff

/*	SYR_CTL	*/
 #define R0362_SYR_CTL 0x0091
 #define F0362_SICTH_ENABLE 0x00910080
 #define F0362_LONG_ECHO 0x00910078
 #define F0362_AUTO_LE_EN 0x00910004
 #define F0362_SYR_BYPASS 0x00910002
 #define F0362_SYR_TR_DIS 0x00910001

/*	SYR_STAT	*/
 #define R0362_SYR_STAT 0x0092
 #define F0362_SYR_LOCKED_STAT 0x00920010
 #define F0362_SYR_MODE 0x00920004
 #define F0362_SYR_GUARD 0x00920003

/*	SYR_NCO1	*/
 #define R0362_SYR_NCO1 0x0093
 #define F0362_SYR_NCO_LO 0x009300ff

/*	SYR_NCO2	*/
 #define R0362_SYR_NCO2 0x0094
 #define F0362_SYR_NCO_HI 0x0094003f

/*	SYR_OFFSET1	*/
 #define R0362_SYR_OFFSET1 0x0095
 #define F0362_SYR_OFFSET_LO 0x009500ff

/*	SYR_OFFSET2	*/
 #define R0362_SYR_OFFSET2 0x0096
 #define F0362_SYR_OFFSET_HI 0x0096003f

/*	FFT_CTL	*/
 #define R0362_FFT_CTL 0x0097
 #define F0362_SHIFT_FFT_TRIG 0x00970018
 #define F0362_FFT_TRIGGER 0x00970004
 #define F0362_FFT_MANUAL 0x00970002
 #define F0362_IFFT_MODE 0x00970001

/*	SCR_CTL	*/
 #define R0362_SCR_CTL 0x0098
 #define F0362_SYRADJDECAY 0x00980070
 #define F0362_SCR_CPEDIS 0x00980002
 #define F0362_SCR_DIS 0x00980001

/*	PPM_CTL1	*/
 #define R0362_PPM_CTL1 0x0099
 #define F0362_MEAN_OFF 0x00990080
 #define F0362_GRAD_OFF 0x00990040
 #define F0362_PPM_MAXFREQ 0x00990030
 #define F0362_PPM_MAXTIM 0x00990008
 #define F0362_PPM_INVSEL 0x00990004
 #define F0362_PPM_SCATDIS 0x00990002
 #define F0362_PPM_BYP 0x00990001

/*	TRL_CTL	*/
 #define R0362_TRL_CTL 0x009a
 #define F0362_TRL_NOMRATE_LSB 0x009a0080
 #define F0362_TRL_GAIN_FACTOR 0x009a0078
 #define F0362_TRL_LOOPGAIN 0x009a0007

/*	TRL_NOMRATE1	*/
 #define R0362_TRL_NOMRATE1 0x009b
 #define F0362_TRL_NOMRATE_LO 0x009b00ff

/*	TRL_NOMRATE2	*/
 #define R0362_TRL_NOMRATE2 0x009c
 #define F0362_TRL_NOMRATE_HI 0x009c00ff

/*	TRL_TIME1	*/
 #define R0362_TRL_TIME1 0x009d
 #define F0362_TRL_TOFFSET_LO 0x009d00ff

/*	TRL_TIME2	*/
 #define R0362_TRL_TIME2 0x009e
 #define F0362_TRL_TOFFSET_HI 0x009e00ff

/*	CRL_CTL	*/
 #define R0362_CRL_CTL 0x009f
 #define F0362_CRL_DIS 0x009f0080
 #define F0362_CRL_GAIN_FACTOR 0x009f0078
 #define F0362_CRL_LOOPGAIN 0x009f0007

/*	CRL_FREQ1	*/
 #define R0362_CRL_FREQ1 0x00a0
 #define F0362_CRL_FOFFSET_LO 0x00a000ff

/*	CRL_FREQ2	*/
 #define R0362_CRL_FREQ2 0x00a1
 #define F0362_CRL_FOFFSET_HI 0x00a100ff

/*	CRL_FREQ3	*/
 #define R0362_CRL_FREQ3 0x00a2
 #define F0362_CRL_FOFFSET_VHI 0x00a200ff

/*	CHC_CTL1	*/
 #define R0362_CHC_CTL1 0x00a3
 #define F0362_MEAN_PILOT_GAIN 0x00a300e0
 #define F0362_MANMEANP 0x00a30010
 #define F0362_DBADP 0x00a30008
 #define F0362_DNOISEN 0x00a30004
 #define F0362_DCHCPRED 0x00a30002
 #define F0362_CHC_INT 0x00a30001

/*	CHC_SNR	*/
 #define R0362_CHC_SNR 0x00a4
 #define F0362_CHC_SNR 0x00a400ff

/*	BDI_CTL	*/
 #define R0362_BDI_CTL 0x00a5
 #define F0362_BDI_LPSEL 0x00a50002
 #define F0362_BDI_SERIAL 0x00a50001

/*	DMP_CTL	*/
 #define R0362_DMP_CTL 0x00a6
 #define F0362_DMP_SCALING_FACTOR 0x00a6001e
 #define F0362_DMP_SDDIS 0x00a60001

/*	TPS_RCVD1	*/
 #define R0362_TPS_RCVD1 0x00a7
 #define F0362_TPS_CHANGE 0x00a70040
 #define F0362_BCH_OK 0x00a70020
 #define F0362_TPS_SYNC 0x00a70010
 #define F0362_TPS_FRAME 0x00a70003

/*	TPS_RCVD2	*/
 #define R0362_TPS_RCVD2 0x00a8
 #define F0362_TPS_HIERMODE 0x00a80070
 #define F0362_TPS_CONST 0x00a80003

/*	TPS_RCVD3	*/
 #define R0362_TPS_RCVD3 0x00a9
 #define F0362_TPS_LPCODE 0x00a90070
 #define F0362_TPS_HPCODE 0x00a90007

/*	TPS_RCVD4	*/
 #define R0362_TPS_RCVD4 0x00aa
 #define F0362_TPS_GUARD 0x00aa0030
 #define F0362_TPS_MODE 0x00aa0003

/*	TPS_ID_CELL1	*/
 #define R0362_TPS_ID_CELL1 0x00ab
 #define F0362_TPS_ID_CELL_LO 0x00ab00ff

/*	TPS_ID_CELL2	*/
 #define R0362_TPS_ID_CELL2 0x00ac
 #define F0362_TPS_ID_CELL_HI 0x00ac00ff

/*	TPS_RCVD5_SET1	*/
 #define R0362_TPS_RCVD5_SET1 0x00ad
 #define F0362_TPS_NA 0x00ad00fc
 #define F0362_TPS_SETFRAME 0x00ad0003

/*	TPS_SET2	*/
 #define R0362_TPS_SET2 0x00ae
 #define F0362_TPS_SETHIERMODE 0x00ae0070
 #define F0362_TPS_SETCONST 0x00ae0003

/*	TPS_SET3	*/
 #define R0362_TPS_SET3 0x00af
 #define F0362_TPS_SETLPCODE 0x00af0070
 #define F0362_TPS_SETHPCODE 0x00af0007

/*	TPS_CTL	*/
 #define R0362_TPS_CTL 0x00b0
 #define F0362_TPS_IMM 0x00b00004
 #define F0362_TPS_BCHDIS 0x00b00002
 #define F0362_TPS_UPDDIS 0x00b00001

/*	CTL_FFTOSNUM	*/
 #define R0362_CTL_FFTOSNUM 0x00b1
 #define F0362_SYMBOL_NUMBER 0x00b1007f

/*	TESTSELECT	*/
 #define R0362_TESTSELECT 0x00b2
 #define F0362_TESTSELECT 0x00b2001f

/*	MSC_REV	*/
 #define R0362_MSC_REV 0x00b3
 #define F0362_REV_NUMBER 0x00b300ff

/*	PIR_CTL	*/
 #define R0362_PIR_CTL 0x00b4
 #define F0362_FREEZE 0x00b40001

/*	SNR_CARRIER1	*/
 #define R0362_SNR_CARRIER1 0x00b5
 #define F0362_SNR_CARRIER_LO 0x00b500ff

/*	SNR_CARRIER2	*/
 #define R0362_SNR_CARRIER2 0x00b6
 #define F0362_MEAN 0x00b60080
 #define F0362_SNR_CARRIER_HI 0x00b6001f

/*	PPM_CPAMP	*/
 #define R0362_PPM_CPAMP 0x00b7
 #define F0362_PPM_CPC 0x00b700ff

/*	TSM_AP0	*/
 #define R0362_TSM_AP0 0x00b8
 #define F0362_ADDRESS_BYTE_0 0x00b800ff

/*	TSM_AP1	*/
 #define R0362_TSM_AP1 0x00b9
 #define F0362_ADDRESS_BYTE_1 0x00b900ff

/*	TSM_AP2	*/
 #define R0362_TSM_AP2 0x00ba
 #define F0362_DATA_BYTE_0 0x00ba00ff

/*	TSM_AP3	*/
 #define R0362_TSM_AP3 0x00bb
 #define F0362_DATA_BYTE_1 0x00bb00ff

/*	TSM_AP4	*/
 #define R0362_TSM_AP4 0x00bc
 #define F0362_DATA_BYTE_2 0x00bc00ff

/*	TSM_AP5	*/
 #define R0362_TSM_AP5 0x00bd
 #define F0362_DATA_BYTE_3 0x00bd00ff

/*	TSM_AP6	*/
 #define R0362_TSM_AP6 0x00be
 #define F0362_TSM_AP6 0x00be00ff

/*	TSM_AP7	*/
 #define R0362_TSM_AP7 0x00bf
 #define F0362_MEM_SELECT_BYTE 0x00bf00ff

/*	TSTRES	*/
 #define R0362_TSTRES 0x00c0
 #define F0362_FRES_DISPLAY 0x00c00080
 #define F0362_FRES_FIFO_AD 0x00c00020
 #define F0362_FRESRS 0x00c00010
 #define F0362_FRESACS 0x00c00008
 #define F0362_FRESFEC 0x00c00004
 #define F0362_FRES_PRIF 0x00c00002
 #define F0362_FRESCORE 0x00c00001

/*	ANACTRL	*/
 #define R0362_ANACTRL 0x00c1
 #define F0362_BYPASS_XTAL 0x00c10040
 #define F0362_BYPASS_PLLXN 0x00c1000c
 #define F0362_DIS_PAD_OSC 0x00c10002
 #define F0362_STDBY_PLLXN 0x00c10001

/*	TSTBUS	*/
 #define R0362_TSTBUS 0x00c2
 #define F0362_FORCERATE1 0x00c20080
 #define F0362_TSTCKRS 0x00c20040
 #define F0362_TSTCKDIL 0x00c20020
 #define F0362_CFG_TST 0x00c2000f

/*	TSTRATE	*/
 #define R0362_TSTRATE 0x00c6
 #define F0362_FORCEPHA 0x00c60080
 #define F0362_FNEWPHA 0x00c60010
 #define F0362_FROT90 0x00c60008
 #define F0362_FR 0x00c60007

/*	CONSTMODE	*/
 #define R0362_CONSTMODE 0x00cb
 #define F0362_TST_PRIF 0x00cb00e0
 #define F0362_CAR_TYPE 0x00cb0018
 #define F0362_CONST_MODE 0x00cb0003

/*	CONSTCARR1	*/
 #define R0362_CONSTCARR1 0x00cc
 #define F0362_CONST_CARR_LO 0x00cc00ff

/*	CONSTCARR2	*/
 #define R0362_CONSTCARR2 0x00cd
 #define F0362_CONST_CARR_HI 0x00cd001f

/*	ICONSTEL	*/
 #define R0362_ICONSTEL 0x00ce
 #define F0362_ICONSTEL 0x00ce01ff

/*	QCONSTEL	*/
 #define R0362_QCONSTEL 0x00cf
 #define F0362_QCONSTEL 0x00cf01ff

/*	TSTBISTRES0	*/
 #define R0362_TSTBISTRES0 0x00d0
 #define F0362_BEND_BDI 0x00d00080
 #define F0362_BBAD_BDI 0x00d00040
 #define F0362_BEND_PPM 0x00d00020
 #define F0362_BBAD_PPM 0x00d00010
 #define F0362_BEND_SDI 0x00d00008
 #define F0362_BBAD_SDI 0x00d00004
 #define F0362_BEND_INS 0x00d00002
 #define F0362_BBAD_INS 0x00d00001

/*	TSTBISTRES1	*/
 #define R0362_TSTBISTRES1 0x00d1
 #define F0362_BEND_CHC2B 0x00d10080
 #define F0362_BBAD_CHC2B 0x00d10040
 #define F0362_BEND_CHC3 0x00d10020
 #define F0362_BBAD_CHC3 0x00d10010
 #define F0362_BEND_FFTI 0x00d10008
 #define F0362_BBAD_FFTI 0x00d10004
 #define F0362_BEND_FFTW 0x00d10002
 #define F0362_BBAD_FFTW 0x00d10001

/*	TSTBISTRES2	*/
 #define R0362_TSTBISTRES2 0x00d2
 #define F0362_BEND_RS 0x00d20080
 #define F0362_BBAD_RS 0x00d20040
 #define F0362_BEND_SYR 0x00d20020
 #define F0362_BBAD_SYR 0x00d20010
 #define F0362_BEND_CHC1 0x00d20008
 #define F0362_BBAD_CHC1 0x00d20004
 #define F0362_BEND_CHC2 0x00d20002
 #define F0362_BBAD_CHC2 0x00d20001

/*	TSTBISTRES3	*/
 #define R0362_TSTBISTRES3 0x00d3
 #define F0362_BEND_FIFO 0x00d30080
 #define F0362_BBAD_FIFO 0x00d30040
 #define F0362_BEND_VIT2 0x00d30020
 #define F0362_BBAD_VIT2 0x00d30010
 #define F0362_BEND_VIT1 0x00d30008
 #define F0362_BBAD_VIT1 0x00d30004
 #define F0362_BEND_DIL 0x00d30002
 #define F0362_BBAD_DIL 0x00d30001

/*	RF_AGC1	*/
 #define R0362_RF_AGC1 0x00d4
 #define F0362_RF_AGC1_LEVEL_HI 0x00d400ff

/*	RF_AGC2	*/
 #define R0362_RF_AGC2 0x00d5
 #define F0362_REF_ADGP 0x00d50080
 #define F0362_STDBY_ADCGP 0x00d50020
 #define F0362_CHANNEL_SEL 0x00d5001c
 #define F0362_RF_AGC1_LEVEL_LO 0x00d50003

/*	ANADIGCTRL	*/
 #define R0362_ANADIGCTRL 0x00d7
 #define F0362_SEL_CLKDEM 0x00d70020
 #define F0362_ADC_RIS_EGDE 0x00d70004
 #define F0362_SGN_ADC 0x00d70002
 #define F0362_SEL_AD12_SYNC 0x00d70001

/*	PLLMDIV	*/
 #define R0362_PLLMDIV 0x00d8
 #define F0362_PLL_MDIV 0x00d800ff

/*	PLLSETUP	*/
 #define R0362_PLLSETUP 0x00da
 #define F0362_PLL_PDIV 0x00da0070

/*	DUAL_AD12	*/
 #define R0362_DUAL_AD12 0x00db
 #define F0362_FS20M 0x00db0020
 #define F0362_FS50M 0x00db0010
 #define F0362_INMODE 0x00db0008
 #define F0362_POFFQ 0x00db0004
 #define F0362_POFFI 0x00db0002
 #define F0362_POFFREF 0x00db0001

/*	TSTBIST	*/
 #define R0362_TSTBIST 0x00dc
 #define F0362_TST_GCLKENA 0x00dc0020
 #define F0362_TST_MEMBIST 0x00dc001f

/*	PAD_COMP_CTRL	*/
 #define R0362_PAD_COMP_CTRL 0x00dd
 #define F0362_COMPTQ 0x00dd0010
 #define F0362_COMPEN 0x00dd0008
 #define F0362_FREEZE2 0x00dd0004
 #define F0362_SLEEP_INHBT 0x00dd0002
 #define F0362_CHIP_SLEEP 0x00dd0001

/*	PAD_COMP_WR	*/
 #define R0362_PAD_COMP_WR 0x00de
 #define F0362_WR_ASRC 0x00de007f

/*	PAD_COMP_RD	*/
 #define R0362_PAD_COMP_RD 0x00df
 #define F0362_COMPOK 0x00df0080
 #define F0362_RD_ASRC 0x00df007f

/*	GHOSTREG	*/
 #define R0362_GHOSTREG 0x0000
 #define F0362_GHOSTFIELD 0x000000ff


#define		STV0362_NBREGS 208
#define 	STV0362_NBFIELDS 478

#endif