d0362_map.h

st7710的tuner标准驱动

#ifndef H_MAP362



	#define H_MAP362



/*Registers and Fields difinitions*/


/*	PLLNDIV	*/
 #define R0362_PLLNDIV 0x00d9
 #define F0362_PLL_NDIV 0x00d900ff

/*	ID	*/
 #define R0362_ID 0x0000
 #define F0362_IDENTIFICATIONREGISTER 0x000000ff

/*	I2CRPT	*/
 #define R0362_I2CRPT 0x0001
 #define F0362_I2CT_ON 0x00010080
 #define F0362_ENARPT_LEVEL 0x00010070
 #define F0362_SCLT_DELAY 0x00010008
 #define F0362_SCLT_NOD 0x00010004
 #define F0362_STOP_ENABLE 0x00010002
 #define F0362_SDAT_NOD 0x00010001

/*	TOPCTRL	*/
 #define R0362_TOPCTRL 0x0002
 #define F0362_STDBY 0x00020080
 #define F0362_STDBY_FEC 0x00020040
 #define F0362_STDBY_CORE 0x00020020
 #define F0362_DIR_CLK_54 0x00020010
 #define F0362_TS_DIS 0x00020008
 #define F0362_DIR_CLK_108 0x00020004
 #define F0362_TUNER_BB 0x00020002
 #define F0362_DVBT_H 0x00020001

/*	IOCFG0	*/
 #define R0362_IOCFG0 0x0003
 #define F0362_OP0_SD 0x00030080
 #define F0362_OP0_VAL 0x00030040
 #define F0362_OP0_OD 0x00030020
 #define F0362_OP0_INV 0x00030010
 #define F0362_OP0_DACVALUE_HI 0x0003000f

/*	DAC0R	*/
 #define R0362_DAC0R 0x0004
 #define F0362_OP0_DACVALUE_LO 0x000400ff

/*	IOCFG1	*/
 #define R0362_IOCFG1 0x0005
 #define F0362_IP0 0x00050040
 #define F0362_OP1_OD 0x00050020
 #define F0362_OP1_INV 0x00050010
 #define F0362_OP1_DACVALUE_HI 0x0005000f

/*	DAC1R	*/
 #define R0362_DAC1R 0x0006
 #define F0362_OP1_DACVALUE_LO 0x000600ff

/*	IOCFG2	*/
 #define R0362_IOCFG2 0x0007
 #define F0362_OP2_LOCK_CONF 0x000700e0
 #define F0362_OP2_OD 0x00070010
 #define F0362_OP2_VAL 0x00070008
 #define F0362_OP1_LOCK_CONF 0x00070007

/*	SDFR	*/
 #define R0362_SDFR 0x0008
 #define F0362_OP0_FREQ 0x000800f0
 #define F0362_OP1_FREQ 0x0008000f

/*	STATUS	*/
 #define R0362_STATUS 0x0009
 #define F0362_TPS_LOCK 0x00090080
 #define F0362_SYR_LOCK 0x00090040
 #define F0362_AGC_LOCK 0x00090020
 #define F0362_PRF 0x00090010
 #define F0362_LK 0x00090008
 #define F0362_PR 0x00090007

/*	AUX_CLK	*/
 #define R0362_AUX_CLK 0x000a
 #define F0362_AUXFEC_CTL 0x000a00c0
 #define F0362_DIS_CKX4 0x000a0020
 #define F0362_CKSEL 0x000a0018
 #define F0362_CKDIV_PROG 0x000a0006
 #define F0362_AUXCLK_ENA 0x000a0001

/*	FREESYS1	*/
 #define R0362_FREESYS1 0x000b
 #define F0362_FREESYS1 0x000b00ff

/*	FREESYS2	*/
 #define R0362_FREESYS2 0x000c
 #define F0362_FREESYS2 0x000c00ff

/*	FREESYS3	*/
 #define R0362_FREESYS3 0x000d
 #define F0362_FREESYS3 0x000d00ff

/*	AGC2MAX	*/
 #define R0362_AGC2MAX 0x0010
 #define F0362_AGC2MAX 0x001000ff

/*	AGC2MIN	*/
 #define R0362_AGC2MIN 0x0011
 #define F0362_AGC2MIN 0x001100ff

/*	AGC1MAX	*/
 #define R0362_AGC1MAX 0x0012
 #define F0362_AGC1MAX 0x001200ff

/*	AGC1MIN	*/
 #define R0362_AGC1MIN 0x0013
 #define F0362_AGC1MIN 0x001300ff

/*	AGCR	*/
 #define R0362_AGCR 0x0014
 #define F0362_RATIO_A 0x001400e0
 #define F0362_RATIO_B 0x00140018
 #define F0362_RATIO_C 0x00140007

/*	AGC2TH	*/
 #define R0362_AGC2TH 0x0015
 #define F0362_AGC2_THRES 0x001500ff

/*	AGC12C	*/
 #define R0362_AGC12C 0x0016
 #define F0362_AGC1_IV 0x00160080
 #define F0362_AGC1_OD 0x00160040
 #define F0362_AGC1_LOAD 0x00160020
 #define F0362_AGC2_IV 0x00160010
 #define F0362_AGC2_OD 0x00160008
 #define F0362_AGC2_LOAD 0x00160004
 #define F0362_AGC12_MODE 0x00160003

/*	AGCCTRL1	*/
 #define R0362_AGCCTRL1 0x0017
 #define F0362_DAGC_ON 0x00170080
 #define F0362_INVERT_AGC12 0x00170040
 #define F0362_AGC1_MODE 0x00170008
 #define F0362_AGC2_MODE 0x00170007

/*	AGCCTRL2	*/
 #define R0362_AGCCTRL2 0x0018
 #define F0362_FRZ2_CTRL 0x00180060
 #define F0362_FRZ1_CTRL 0x00180018
 #define F0362_TIME_CST 0x00180007

/*	AGC1VAL1	*/
 #define R0362_AGC1VAL1 0x0019
 #define F0362_AGC1_VAL_LO 0x001900ff

/*	AGC1VAL2	*/
 #define R0362_AGC1VAL2 0x001a
 #define F0362_AGC1_VAL_HI 0x001a000f

/*	AGC2VAL1	*/
 #define R0362_AGC2VAL1 0x001b
 #define F0362_AGC2_VAL_LO 0x001b00ff

/*	AGC2VAL2	*/
 #define R0362_AGC2VAL2 0x001c
 #define F0362_AGC2_VAL_HI 0x001c000f

/*	AGC2PGA	*/
 #define R0362_AGC2PGA 0x001d
 #define F0362_AGC2PGA 0x001d00ff

/*	OVF_RATE1	*/
 #define R0362_OVF_RATE1 0x001e
 #define F0362_OVF_RATE_HI 0x001e000f

/*	OVF_RATE2	*/
 #define R0362_OVF_RATE2 0x001f
 #define F0362_OVF_RATE_LO 0x001f00ff

/*	GAIN_SRC1	*/
 #define R0362_GAIN_SRC1 0x0020
 #define F0362_INV_SPECTR 0x00200080
 #define F0362_IQ_INVERT 0x00200040
 #define F0362_INR_BYPASS 0x00200020
 #define F0362_INS_BYPASS 0x00200010
 #define F0362_GAIN_SRC_HI 0x0020000f

/*	GAIN_SRC2	*/
 #define R0362_GAIN_SRC2 0x0021
 #define F0362_GAIN_SRC_LO 0x002100ff

/*	INC_DEROT1	*/
 #define R0362_INC_DEROT1 0x0022
 #define F0362_INC_DEROT_HI 0x002200ff

/*	INC_DEROT2	*/
 #define R0362_INC_DEROT2 0x0023
 #define F0362_INC_DEROT_LO 0x002300ff

/*	PPM_CPAMP_DIR	*/
 #define R0362_PPM_CPAMP_DIR 0x0024
 #define F0362_PPM_CPAMP_DIRECT 0x002400ff

/*	PPM_CPAMP_INV	*/
 #define R0362_PPM_CPAMP_INV 0x0025
 #define F0362_PPM_CPAMP_INV 0x002500ff

/*	FREESTFE_1	*/
 #define R0362_FREESTFE_1 0x0026
 #define F0362_SYMBOL_NUMBER_INC 0x002600c0
 #define F0362_SEL_LSB 0x00260004
 #define F0362_AVERAGE_ON 0x00260002
 #define F0362_DC_ADJ 0x00260001

/*	FREESTFE_2	*/
 #define R0362_FREESTFE_2 0x0027
 #define F0362_SEL_SRCOUT 0x002700c0
 #define F0362_SEL_SYRTHR 0x0027001f

/*	DCOFFSET	*/
 #define R0362_DCOFFSET 0x0028
 #define F0362_SELECT_I_Q 0x00280080
 #define F0362_DC_OFFSET 0x0028007f

/*	EN_PROCESS	*/
 #define R0362_EN_PROCESS 0x0029
 #define F0362_INS_NIN_INDEX 0x002900f0
 #define F0362_ENAB_MANUAL 0x00290001

/*	SDI_SMOOTHER	*/
 #define R0362_SDI_SMOOTHER 0x002a
 #define F0362_DIS_SMOOTH 0x002a0080
 #define F0362_SDI_INC_SMOOTHER 0x002a007f

/*	FE_LOOP_OPEN	*/
 #define R0362_FE_LOOP_OPEN 0x002b
 #define F0362_TRL_LOOP_OP 0x002b0002
 #define F0362_CRL_LOOP_OP 0x002b0001

/*	FREQOFF1	*/
 #define R0362_FREQOFF1 0x002c
 #define F0362_FREQ_OFFSET_LOOP_OPEN_VHI 0x002c00ff

/*	FREQOFF2	*/
 #define R0362_FREQOFF2 0x002d
 #define F0362_FREQ_OFFSET_LOOP_OPEN_HI 0x002d00ff

/*	FREQOFF3	*/
 #define R0362_FREQOFF3 0x002e
 #define F0362_FREQ_OFFSET_LOOP_OPEN_LO 0x002e00ff

/*	TIMOFF1	*/
 #define R0362_TIMOFF1 0x002f
 #define F0362_TIM_OFFSET_LOOP_OPEN_HI 0x002f00ff

/*	TIMOFF2	*/
 #define R0362_TIMOFF2 0x0030
 #define F0362_TIM_OFFSET_LOOP_OPEN_LO 0x003000ff

/*	EPQ	*/
 #define R0362_EPQ 0x0031
 #define F0362_EPQ 0x003100ff

/*	EPQAUTO	*/
 #define R0362_EPQAUTO 0x0032
 #define F0362_EPQ2 0x003200ff

/*	CHP_TAPS	*/
 #define R0362_CHP_TAPS 0x0033
 #define F0362_SCAT_FILT_EN 0x00330002
 #define F0362_TAPS_EN 0x00330001

/*	CHP_DYN_COEFF	*/
 #define R0362_CHP_DYN_COEFF 0x0034
 #define F0362_CHP_DYNAM_COEFFCIENT 0x003400ff

/*	PPM_STATE_MAC	*/
 #define R0362_PPM_STATE_MAC 0x0035
 #define F0362_PPM_STATE_MACHINE_DECODER 0x0035003f

/*	INR_THRESHOLD	*/
 #define R0362_INR_THRESHOLD 0x0036
 #define F0362_INR_THRESHOLD 0x003600ff

/*	EPQ_TPS_ID_CELL	*/
 #define R0362_EPQ_TPS_ID_CELL 0x0037
 #define F0362_DIS_TPS_RSVD 0x00370040
 #define F0362_DIS_BCH 0x00370020
 #define F0362_DIS_ID_CEL 0x00370010
 #define F0362_HOLD_SLOPE 0x00370008
 #define F0362_TPS_ADJUST_SYM 0x00370007

/*	EPQ_CFG	*/
 #define R0362_EPQ_CFG 0x0038
 #define F0362_EPQ_RANGE 0x00380002
 #define F0362_EPQ_SOFT 0x00380001

/*	EPQ_STATUS	*/
 #define R0362_EPQ_STATUS 0x0039
 #define F0362_SLOPE_INC 0x003900fc
 #define F0362_TPS_FIELD 0x00390003

/*	FECM	*/
 #define R0362_FECM 0x0040
 #define F0362_FEC_MODE 0x004000f0
 #define F0362_VIT_DIFF 0x00400004
 #define F0362_SYNC 0x00400002
 #define F0362_SYM 0x00400001

/*	VTH0	*/
 #define R0362_VTH0 0x0041
 #define F0362_VTH0 0x0041007f

/*	VTH1	*/
 #define R0362_VTH1 0x0042
 #define F0362_VTH1 0x0042007f

/*	VTH2	*/
 #define R0362_VTH2 0x0043
 #define F0362_VTH2 0x0043007f

/*	VTH3	*/
 #define R0362_VTH3 0x0044
 #define F0362_VTH3 0x0044007f

/*	VTH4	*/
 #define R0362_VTH4 0x0045
 #define F0362_VTH4 0x0045007f

/*	VTH5	*/
 #define R0362_VTH5 0x0046
 #define F0362_VTH5 0x0046007f

/*	FREEVIT	*/
 #define R0362_FREEVIT 0x0047
 #define F0362_FREEVIT 0x004700ff

/*	VITPROG	*/
 #define R0362_VITPROG 0x0049
 #define F0362_FORCE_ROTA 0x004900c0
 #define F0362_AUTO_FREEZE 0x00490030
 #define F0362_MDIVIDER 0x00490003

/*	PR	*/
 #define R0362_PR 0x004a
 #define F0362_FRAPTCR 0x004a0080
 #define F0362_E7_8 0x004a0020
 #define F0362_E6_7 0x004a0010
 #define F0362_E5_6 0x004a0008
 #define F0362_E3_4 0x004a0004
 #define F0362_E2_3 0x004a0002
 #define F0362_E1_2 0x004a0001

/*	VSEARCH	*/
 #define R0362_VSEARCH 0x004b
 #define F0362_PR_AUTO 0x004b0080
 #define F0362_PR_FREEZE 0x004b0040
 #define F0362_SAMPNUM 0x004b0030
 #define F0362_TIMEOUT 0x004b000c
 #define F0362_HYSTER 0x004b0003

/*	RS	*/
 #define R0362_RS 0x004c
 #define F0362_DEINT_ENA 0x004c0080
 #define F0362_OUTRS_SP 0x004c0040
 #define F0362_RS_ENA 0x004c0020
 #define F0362_DESCR_ENA 0x004c0010
 #define F0362_ERRBIT_ENA 0x004c0008
 #define F0362_FORCE47 0x004c0004
 #define F0362_CLK_POL 0x004c0002
 #define F0362_CLK_CFG 0x004c0001

/*	RSOUT	*/
 #define R0362_RSOUT 0x004d
 #define F0362_ENA_STBACKEND 0x004d0010
 #define F0362_ENA8_LEVEL 0x004d000f

/*	ERRCTRL1	*/
 #define R0362_ERRCTRL1 0x004e
 #define F0362_ERRMODE1 0x004e0080
 #define F0362_TESTERS1 0x004e0040
 #define F0362_ERR_SOURCE1 0x004e0030
 #define F0362_RESET_CNTR1 0x004e0004
 #define F0362_NUM_EVENT1 0x004e0003

/*	ERRCNTM1	*/
 #define R0362_ERRCNTM1 0x004f
 #define F0362_ERROR_COUNT1_HI 0x004f00ff

/*	ERRCNTL1	*/
 #define R0362_ERRCNTL1 0x0050
 #define F0362_ERROR_COUNT1_LO 0x005000ff

/*	ERRCTRL2	*/
 #define R0362_ERRCTRL2 0x0051
 #define F0362_ERRMODE2 0x00510080
 #define F0362_TESTERS2 0x00510040
 #define F0362_ERR_SOURCE2 0x00510030
 #define F0362_RESET_CNTR2 0x00510004
 #define F0362_NUM_EVENT2 0x00510003

/*	ERRCNTM2	*/
 #define R0362_ERRCNTM2 0x0052
 #define F0362_ERROR_COUNT2_HI 0x005200ff

/*	ERRCNTL2	*/
 #define R0362_ERRCNTL2 0x0053
 #define F0362_ERROR_COUNT2_LO 0x005300ff

/*	FREEDRS	*/
 #define R0362_FREEDRS 0x0054
 #define F0362_FREEDRS 0x005400ff

/*	VERROR	*/
 #define R0362_VERROR 0x0055
 #define F0362_ERROR_VALUE 0x005500ff

/*	ERRCTRL3	*/
 #define R0362_ERRCTRL3 0x0056
 #define F0362_ERRMODE3 0x00560080
 #define F0362_TESTERS3 0x00560040
 #define F0362_ERR_SOURCE3 0x00560030
 #define F0362_RESET_CNTR3 0x00560004
 #define F0362_NUM_EVENT3 0x00560003

/*	ERRCNTM3	*/
 #define R0362_ERRCNTM3 0x0057
 #define F0362_ERROR_COUNT3_HI 0x005700ff

/*	ERRCNTL3	*/
 #define R0362_ERRCNTL3 0x0058
 #define F0362_ERROR_COUNT3_LO 0x005800ff

/*	DILSTK1	*/
 #define R0362_DILSTK1 0x0059
 #define F0362_DILSTK_HI 0x005900ff

/*	DILSTK0	*/
 #define R0362_DILSTK0 0x005a
 #define F0362_DILSTK_LO 0x005a00ff

/*	DILBWSTK1	*/
 #define R0362_DILBWSTK1 0x005b
 #define F0362_DILBWSTK1 0x005b00ff

/*	DILBWST0	*/
 #define R0362_DILBWST0 0x005c
 #define F0362_DILBWST0 0x005c00ff

/*	LNBRX	*/
 #define R0362_LNBRX 0x005d
 #define F0362_LINE_OK 0x005d0080
 #define F0362_OCCURRED_ERR 0x005d0040
 #define F0362_RSOV_DATAIN 0x005d0008
 #define F0362_LNBTX_CHIPADDR 0x005d0007

/*	RSTC	*/
 #define R0362_RSTC 0x005e
 #define F0362_DEINTTC 0x005e0080
 #define F0362_DIL64_ON 0x005e0040
 #define F0362_RSTC 0x005e0020
 #define F0362_DESCRAMTC 0x005e0010
 #define F0362_MODSYNCBYT 0x005e0004
 #define F0362_LOWP_DIS 0x005e0002
 #define F0362_HIGHP_DIS 0x005e0001

/*	VIT_BIST	*/
 #define R0362_VIT_BIST 0x005f
 #define F0362_RAND_RAMP 0x005f0040
 #define F0362_NOISE_LEVEL 0x005f0038
 #define F0362_PR_VIT_BIST 0x005f0007

/*	IIR_CELL_NB	*/
 #define R0362_IIR_CELL_NB 0x0060
 #define F0362_NRST_IIR 0x00600080
 #define F0362_IIR_CELL_NB 0x00600007

/*	IIR_CX_COEFF1_MSB	*/
 #define R0362_IIR_CX_COEFF1_MSB 0x0061
 #define F0362_IIR_CX_COEFF1_MSB 0x006100ff

/*	IIR_CX_COEFF1_LSB	*/
 #define R0362_IIR_CX_COEFF1_LSB 0x0062
 #define F0362_IIR_CX_COEFF1_LSB 0x006200ff

/*	IIR_CX_COEFF2_MSB	*/
 #define R0362_IIR_CX_COEFF2_MSB 0x0063
 #define F0362_IIR_CX_COEFF2_MSB 0x006300ff

/*	IIR_CX_COEFF2_LSB	*/
 #define R0362_IIR_CX_COEFF2_LSB 0x0064
 #define F0362_IIR_CX_COEFF2_LSB 0x006400ff

/*	IIR_CX_COEFF3_MSB	*/
 #define R0362_IIR_CX_COEFF3_MSB 0x0065
 #define F0362_IIR_CX_COEFF3_MSB 0x006500ff

/*	IIR_CX_COEFF3_LSB	*/
 #define R0362_IIR_CX_COEFF3_LSB 0x0066
 #define F0362_IIR_CX_COEFF3_LSB 0x006600ff

/*	IIR_CX_COEFF4_MSB	*/
 #define R0362_IIR_CX_COEFF4_MSB 0x0067
 #define F0362_IIR_CX_COEFF4_MSB 0x006700ff

/*	IIR_CX_COEFF4_LSB	*/
 #define R0362_IIR_CX_COEFF4_LSB 0x0068
 #define F0362_IIR_CX_COEFF4_LSB 0x006800ff

/*	IIR_CX_COEFF5_MSB	*/
 #define R0362_IIR_CX_COEFF5_MSB 0x0069
 #define F0362_IIR_CX_COEFF5_MSB 0x006900ff

/*	IIR_CX_COEFF5_LSB	*/
 #define R0362_IIR_CX_COEFF5_LSB 0x006a
 #define F0362_IIR_CX_COEFF5_LSB 0x006a00ff

/*	FEPATH_CFG	*/
 #define R0362_FEPATH_CFG 0x006b
 #define F0362_DEMUX_SWAP 0x006b0004
 #define F0362_DIGAGC_SWAP 0x006b0002
 #define F0362_LONGPATH_IF 0x006b0001

/*	PMC1_FUNC	*/
 #define R0362_PMC1_FUNC 0x006c
 #define F0362_SOFT_RSTN 0x006c0080
 #define F0362_PMC1_AVERAGE_TIME 0x006c0078
 #define F0362_PMC1_WAIT_TIME 0x006c0006
 #define F0362_PMC1_2N_SEL 0x006c0001

/*	PMC1_FORCE	*/
 #define R0362_PMC1_FORCE 0x006d
 #define F0362_PMC1_FORCE 0x006d0080
 #define F0362_PMC1_FORCE_VALUE 0x006d007c

/*	PMC2_FUNC	*/
 #define R0362_PMC2_FUNC 0x006e
 #define F0362_PMC2_SOFT_STN 0x006e0080
 #define F0362_PMC2_ACCU_TIME 0x006e0070
 #define F0362_PMC2_CMDP_MN 0x006e0008
 #define F0362_PMC2_SWAP 0x006e0004

/*	DIG_AGC_R	*/
 #define R0362_DIG_AGC_R 0x0070
 #define F0362_COM_SOFT_RSTN 0x00700080
 #define F0362_COM_AGC_ON 0x00700040
 #define F0362_COM_EARLY 0x00700020
 #define F0362_AUT_SOFT_RESETN 0x00700010
 #define F0362_AUT_AGC_ON 0x00700008
 #define F0362_AUT_EARLY 0x00700004
 #define F0362_AUT_ROT_EN 0x00700002
 #define F0362_LOCK_SOFT_RESETN 0x00700001

/*	COMAGC_TARMSB	*/
 #define R0362_COMAGC_TARMSB 0x0071
 #define F0362_COM_AGC_TARGET_MSB 0x007100ff

/*	COM_AGC_TAR_ENMODE	*/
 #define R0362_COM_AGC_TAR_ENMODE 0x0072