361_map.h

st7710的tuner标准驱动

#ifndef H_MAP361



	#define H_MAP361




/* ID */
 #define R_ID 0x0
 #define IDENTIFICATIONREGISTER 0xff

/* I2CRPT */
 #define R_I2CRPT 0x1
 #define I2CT_ON 0x10080
 #define ENARPT_LEVEL 0x10070
 #define SCLT_DELAY 0x10008
 #define SCLT_NOD 0x10004
 #define STOP_ENABLE 0x10002
 #define SDAT_NOD 0x10001

/* TOPCTRL */
 #define R_TOPCTRL 0x2
 #define STDBY 0x20080
 #define STDBY_FEC 0x20040
 #define STDBY_CORE 0x20020
 #define DIR_CLK 0x20010
 #define TS_DIS 0x20008
 #define DUAL_CKDIR 0x20004
 #define BYP_BUFFER 0x20002
 #define ENA_27 0x20001

/* IOCFG0 */
 #define R_IOCFG0 0x3
 #define OP0_SD 0x30080
 #define OP0_VAL 0x30040
 #define OP0_OD 0x30020
 #define OP0_INV 0x30010
 #define OP0_DACVALUE_HI 0x3000f

/* DAC0R */
 #define R_DAC0R 0x4
 #define OP0_DACVALUE_LO 0x400ff

/* IOCFG1 */
 #define R_IOCFG1 0x5
 #define IP0 0x50040
 #define OP1_OD 0x50020
 #define OP1_INV 0x50010
 #define OP1_DACVALUE_HI 0x5000f


/* DAC1R */
 #define R_DAC1R 0x6
 #define OP1_DACVALUE_LO 0x600ff

/* IOCFG2 */
 #define R_IOCFG2 0x7
 #define OP2_LOCK_CONF 0x700e0
 #define OP2_OD 0x70010
 #define OP2_VAL 0x70008
 #define OP1_LOCK_CONF 0x70007

/* SDFR */
 #define R_SDFR 0x8
 #define OP0_FREQ 0x800f0
 #define OP1_FREQ 0x8000f

/* STATUS */
 #define R_STATUS 0x9
 #define TPS_LOCK 0x90080
 #define SYR_LOCK 0x90040
 #define AGC_LOCK 0x90020
 #define PRF 0x90010
 #define LK 0x90008
 #define PR 0x90007

/* AUX_CLK */
 #define R_AUX_CLK 0xa
 #define AUXFEC_CTL 0xa00c0
 #define DIS_CKX4 0xa0020
 #define CKSEL 0xa0018
 #define CKDIV_PROG 0xa0006
 #define AUXCLK_ENA 0xa0001

/* RESERVED_1 */
 #define R_RESERVED_1 0xb

/* RESERVED_2 */
 #define R_RESERVED_2 0xc



/* RESERVED_3 */
 #define R_RESERVED_3 0xd


/* AGC2MAX */
 #define R_AGC2MAX 0x10
 #define AGC2MAX 0x1000ff

/* AGC2MIN */
 #define R_AGC2MIN 0x11
 #define AGC2MIN 0x1100ff

/* AGC1MAX */
 #define R_AGC1MAX 0x12
 #define AGC1MAX 0x1200ff

/* AGC1MIN */
 #define R_AGC1MIN 0x13
 #define AGC1MIN 0x1300ff

/* AGCR */
 #define R_AGCR 0x14
 #define RATIO_A 0x1400e0
 #define RATIO_B 0x140018
 #define RATIO_C 0x140007

/* AGC2TH */
 #define R_AGC2TH 0x15
 #define AGC2_THRES 0x1500ff

/* AGC12C */
 #define R_AGC12C 0x16
 #define AGC1_IV 0x160080
 #define AGC1_OD 0x160040
 #define AGC1_LOAD 0x160020
 #define AGC2_IV 0x160010
 #define AGC2_OD 0x160008
 #define AGC2_LOAD 0x160004
 #define AGC12_MODE 0x160003

/* AGCCTRL1 */
 #define R_AGCCTRL1 0x17
 #define DAGC_ON 0x170080
 #define INVERT_AGC12 0x170040
 #define AGC1_MODE 0x170008
 #define AGC2_MODE 0x170007


/* AGCCTRL2 */
 #define R_AGCCTRL2 0x18
 #define FRZ2_CTRL 0x180060
 #define FRZ1_CTRL 0x180018
 #define TIME_CST 0x180007


/* AGC1VAL1 */
 #define R_AGC1VAL1 0x19
 #define AGC1_VAL_LO 0x1900ff

/* AGC1VAL2 */
 #define R_AGC1VAL2 0x1a
 #define AGC1_VAL_HI 0x1a000f


/* AGC2VAL1 */
 #define R_AGC2VAL1 0x1b
 #define AGC2_VAL_LO 0x1b00ff

/* AGC2VAL2 */
 #define R_AGC2VAL2 0x1c
 #define AGC2_VAL_HI 0x1c000f


/* AGC2PGA */
 #define R_AGC2PGA 0x1d
 #define UAGC2PGA 0x1d003f


/* OVF_RATE1 */
 #define R_OVF_RATE1 0x1e
 #define OVF_RATE_HI 0x1e000f


/* OVF_RATE2 */
 #define R_OVF_RATE2 0x1f
 #define OVF_RATE_LO 0x1f00ff

/* GAIN_SRC1 */
 #define R_GAIN_SRC1 0x20
 #define INV_SPECTR 0x200080
 #define IQ_INVERT 0x200040
 #define INR_BYPASS 0x200020
 #define INS_BYPASS 0x200010
 #define GAIN_SRC_HI 0x20000f

/* GAIN_SRC2 */
 #define R_GAIN_SRC2 0x21
 #define GAIN_SRC_LO 0x2100ff

/* INC_DEROT1 */
 #define R_INC_DEROT1 0x22
 #define INC_DEROT_HI 0x2200ff

/* INC_DEROT2 */
 #define R_INC_DEROT2 0x23
 #define INC_DEROT_LO 0x2300ff

/* PPM_CPAMP_DIR */
 #define R_PPM_CPAMP_DIR 0x24
 #define PPM_CPAMP_DIRECT 0x2400ff

/* PPM_CPAMP_INV */
 #define R_PPM_CPAMP_INV 0x25
 #define PPM_CPAMP_INV 0x2500ff

/* FREESTFE_1 */
 #define R_FREESTFE_1 0x26
 #define SYMBOL_NUMBER_INC 0x2600c0
 #define SEL_LSB 0x260004
 #define AVERAGE_ON 0x260002
 #define DC_ADJ 0x260001


/* FREESTFE_2 */
 #define R_FREESTFE_2 0x27
 #define SEL_SRCOUT 0x2700c0
 #define SEL_SYRTHR 0x27001f


/* DCOFFSET */
 #define R_DCOFFSET 0x28
 #define DC_OFFSET 0x28007f


/* EN_PROCESS */
 #define R_EN_PROCESS 0x29
 #define INS_NIN_INDEX 0x2900f0
 #define ENAB_MANUAL 0x290001

/* RESERVED_4 */
 #define R_RESERVED_4 0x2a
 #define DIS_SMOOTH 0x2a0080
 #define SDI_INC_SMOOTHER 0x2a007f


/* RESERVED_5 */
 #define R_RESERVED_5 0x2b
 #define TRL_LOOP_OP 0x2b0002
 #define CRL_LOOP_OP 0x2b0001


/* RESERVED_6 */
 #define R_RESERVED_6 0x2c
 #define FREQ_OFFSET_LOOP_OPEN_VHI 0x2c00ff

/* RESERVED_7 */
 #define R_RESERVED_7 0x2d
 #define FREQ_OFFSET_LOOP_OPEN_HI 0x2d00ff

/* RESERVED_8 */
 #define R_RESERVED_8 0x2e
 #define FREQ_OFFSET_LOOP_OPEN_LO 0x2e00ff

/* RESERVED_9 */
 #define R_RESERVED_9 0x2f
 #define TIM_OFFSET_LOOP_OPEN_HI 0x2f00ff

/* RESERVED_10 */
 #define R_RESERVED_10 0x30
 #define TIM_OFFSET_LOOP_OPEN_LO 0x3000ff

/* EPQ */
 #define R_EPQ 0x31
 #define EPQ 0x3100ff

/* EPQAUTO */
 #define R_EPQAUTO 0x32
 #define EPQ2 0x3200ff

/* CHP_TAPS */
 #define R_CHP_TAPS 0x33
 #define SCAT_FILT_EN 0x330002
 #define TAPS_EN 0x330001


/* CHP_DYN_COEFF */
 #define R_CHP_DYN_COEFF 0x34
 #define CHP_DYNAM_COEFFCIENT 0x340080


/* PPM_STATE_MAC */
 #define R_PPM_STATE_MAC 0x35
 #define PPM_STATE_MACHINE_DECODER 0x350020



/* INR_THRESHOLD */
 #define R_INR_THRESHOLD 0x36
 #define INR_THRESHOLD 0x360080



/* COR_CTL */
 #define R_COR_CTL 0x80
 #define CORE_ACTIVE 0x800020
 #define HOLD 0x800010
 #define CORE_STATE_CTL 0x80000f


/* COR_STAT */
 #define R_COR_STAT 0x81
 #define SCATT_LOCKED 0x810080
 #define TPS_LOCKED 0x810040
 #define SYR_LOCKED_COR 0x810020
 #define AGC_LOCKED_STAT 0x810010
 #define CORE_STATE_STAT 0x81000f

/* COR_INTEN */
 #define R_COR_INTEN 0x82
 #define INTEN 0x820080
 #define INTEN_SYR 0x820020
 #define INTEN_FFT 0x820010
 #define INTEN_AGC 0x820008
 #define INTEN_TPS1 0x820004
 #define INTEN_TPS2 0x820002
 #define INTEN_TPS3 0x820001

/* COR_INTSTAT */
 #define R_COR_INTSTAT 0x83
 #define INTSTAT_SYR 0x830020
 #define INTSTAT_FFT 0x830010
 #define INTSAT_AGC 0x830008
 #define INTSTAT_TPS1 0x830004
 #define INTSTAT_TPS2 0x830002
 #define INTSTAT_TPS3 0x830001


/* COR_MODEGUARD */
 #define R_COR_MODEGUARD 0x84
 #define FORCE 0x840008
 #define MODE 0x840004
 #define GUARD 0x840003


/* AGC_CTL */
 #define R_AGC_CTL 0x85
 #define AGC_TIMING_FACTOR 0x8500c0
 #define AGC_LAST 0x850010
 #define AGC_GAIN 0x850008
 #define AGC_NEG 0x850004
 #define AGC_SET 0x850002



/* RESERVED_11 */
 #define R_RESERVED_11 0x86
 #define AGC_VAL_LO 0x8600ff

/* RESERVED_12 */
 #define R_RESERVED_12 0x87
 #define AGC_VAL_HI 0x87000f


/* AGC_TARGET */
 #define R_AGC_TARGET 0x88
 #define AGC_TARGET 0x8800ff

/* AGC_GAIN1 */
 #define R_AGC_GAIN1 0x89
 #define AGC_GAIN_LO 0x8900ff

/* AGC_GAIN2 */
 #define R_AGC_GAIN2 0x8a
 #define AGC_LOCKED_GAIN2 0x8a0010
 #define AGC_GAIN_HI 0x8a000f


/* RESERVED_13 */
 #define R_RESERVED_13 0x8b
 #define ITB_INVERT 0x8b0001


/* RESERVED_14 */
 #define R_RESERVED_14 0x8c
 #define ITB_FREQ_LO 0x8c00ff

/* RESERVED_15 */
 #define R_RESERVED_15 0x8d
 #define ITB_FREQ_HI 0x8d003f


/* CAS_CTL */
 #define R_CAS_CTL 0x8e
 #define CCS_ENABLE 0x8e0080
 #define ACS_DISABLE 0x8e0040
 #define DAGC_DIS 0x8e0020
 #define DAGC_GAIN 0x8e0018
 #define CCSMU 0x8e0007

/* CAS_FREQ */
 #define R_CAS_FREQ 0x8f
 #define CCS_FREQ 0x8f00ff

/* CAS_DAGCGAIN */
 #define R_CAS_DAGCGAIN 0x90
 #define CAS_DAGC_GAIN 0x9000ff

/* SYR_CTL */
 #define R_SYR_CTL 0x91
 #define SICTH_ENABLE 0x910080
 #define LONG_ECHO 0x910078
 #define AUTO_LE_EN 0x910004
 #define SYR_BYPASS 0x910002
 #define SYR_TR_DIS 0x910001

/* SYR_STAT */
 #define R_SYR_STAT 0x92
 #define SYR_LOCKED_STAT 0x920010
 #define SYR_MODE 0x920004
 #define SYR_GUARD 0x920003



/* RESERVED_16 */
 #define R_RESERVED_16 0x93
 #define SYR_NCO_LO 0x9300ff

/* RESERVED_17 */
 #define R_RESERVED_17 0x94
 #define SYR_NCO_HI 0x94003f


/* SYR_OFFSET1 */
 #define R_SYR_OFFSET1 0x95
 #define SYR_OFFSET_LO 0x9500ff

/* SYR_OFFSET2 */
 #define R_SYR_OFFSET2 0x96
 #define SYR_OFFSET_HI 0x96003f


/* RESERVED_18 */
 #define R_RESERVED_18 0x97
 #define SHIFT_FFT_TRIG 0x970018
 #define FFT_TRIGGER 0x970004
 #define FFT_MANUAL 0x970002
 #define IFFT_MODE 0x970001


/* SCR_CTL */
 #define R_SCR_CTL 0x98
 #define SYRADJDECAY 0x980070
 #define SCR_CPEDIS 0x980002
 #define SCR_DIS 0x980001



/* PPM_CTL1 */
 #define R_PPM_CTL1 0x99
 #define MEAN_OFF 0x990080
 #define GRAD_OFF 0x990040
 #define PPM_MAXFREQ 0x990030
 #define PPM_MAXTIM 0x990008
 #define PPM_INVSEL 0x990004
 #define PPM_SCATDIS 0x990002
 #define PPM_BYP 0x990001

/* TRL_CTL */
 #define R_TRL_CTL 0x9a
 #define TRL_NOMRATE_LSB 0x9a0080
 #define TRL_GAIN_FACTOR 0x9a0078
 #define TRL_LOOPGAIN 0x9a0007

/* TRL_NOMRATE1 */
 #define R_TRL_NOMRATE1 0x9b
 #define TRL_NOMRATE_LO 0x9b00ff

/* TRL_NOMRATE2 */
 #define R_TRL_NOMRATE2 0x9c
 #define TRL_NOMRATE_HI 0x9c00ff

/* TRL_TIME1 */
 #define R_TRL_TIME1 0x9d
 #define TRL_TOFFSET_LO 0x9d00ff

/* TRL_TIME2 */
 #define R_TRL_TIME2 0x9e
 #define TRL_TOFFSET_HI 0x9e00ff

/* CRL_CTL */
 #define R_CRL_CTL 0x9f
 #define CRL_DIS 0x9f0080
 #define CRL_GAIN_FACTOR 0x9f0078
 #define CRL_LOOPGAIN 0x9f0007

/* CRL_FREQ1 */
 #define R_CRL_FREQ1 0xa0
 #define CRL_FOFFSET_LO 0xa000ff

/* CRL_FREQ2 */
 #define R_CRL_FREQ2 0xa1
 #define CRL_FOFFSET_HI 0xa100ff

/* CRL_FREQ3 */
 #define R_CRL_FREQ3 0xa2
 #define SEXT 0xa20080
 #define CRL_FOFFSET_VHI 0xa2007f

/* CHC_CTL1 */
 #define R_CHC_CTL1 0xa3
 #define MEAN_PILOT_GAIN 0xa300e0
 #define MANMEANP 0xa30010
 #define DBADP 0xa30008
 #define DNOISEN 0xa30004
 #define DCHCPRED 0xa30002
 #define CHC_INT 0xa30001

/* CHC_SNR */
 #define R_CHC_SNR 0xa4
 #define CHC_SNR 0xa400ff

/* BDI_CTL */
 #define R_BDI_CTL 0xa5
 #define BDI_LPSEL 0xa50002
 #define BDI_SERIAL 0xa50001


/* DMP_CTL */
 #define R_DMP_CTL 0xa6
 #define DMP_SCALING_FACTOR 0xa6001e
 #define DMP_SDDIS 0xa60001


/* TPS_RCVD1 */
 #define R_TPS_RCVD1 0xa7
 #define TPS_CHANGE 0xa70040
 #define BCH_OK 0xa70020
 #define TPS_SYNC 0xa70010
 #define TPS_FRAME 0xa70003