360_map.h

st7710的tuner标准驱动

/*#define RATIO_A 52 
#define RATIO_B 53 
#define RATIO_C 54
*/
/*  AGC2TH  */
#define R_AGC2TH 0x15 
/*#define AGC2_THRES 55 
*/
/*  AGC12C */
#define R_AGC12C3 0x16 
/*#define AGC1_IV 56 
#define AGC1_OD 57 
#define AGC1_LOAD 58 
#define AGC2_IV 59
#define AGC2_OD 60 
#define AGC2_LOAD 61 
#define AGC12_MODE 62 
*/

/*  AGCCTRL1    */
#define R_AGCCTRL1 0x17 
/*#define DAGC_ON 63 
#define F_AGCCTRL1_RESERVED_1 64
#define AGC1_MODE 65 
#define AGC2_MODE 66 
*/

/*  AGCCTRL2    */
#define R_AGCCTRL2 0x18 
/*#define F_AGCCTRL2_RESERVED_1 67
#define FRZ2_CTRL 68
#define FRZ1_CTRL 69 
#define TIME_CST 70
*/
/*  AGC1VAL1    */
#define R_AGC1VAL1 0x19 
#define AGC1_VAL_LO_S 0 

#define AGC1_VAL_LO_L 8

#define AGC1_VAL_LO (R_AGC1VAL1)|(AGC1_VAL_LO_S << 16)|(AGC1_VAL_LO_L << 24) 
/*  AGC1VAL2    */
#define R_AGC1VAL2 0x1a 

/*#define F_AGC1VAL2_RESERVED_1 72*/
#define AGC1_VAL_HI_S 0

#define AGC1_VAL_HI_L 4

#define AGC1_VAL_HI (R_AGC1VAL2)|(AGC1_VAL_HI_S << 16)|(AGC1_VAL_HI_L << 24)
  
/*  AGC2VAL1    */
#define R_AGC2VAL1 0x1b 

#define AGC2_VAL_LO_S 0
 
#define AGC2_VAL_LO_L 8 

#define AGC2_VAL_LO (R_AGC2VAL1)|(AGC2_VAL_LO_S << 16)|(AGC2_VAL_LO_L << 24) 

/*  AGC2VAL2    */
#define R_AGC2VAL2 0x1c
/*#define F_AGC2VAL2_RESERVED_1 75*/

#define AGC2_VAL_HI_S  0 

#define AGC2_VAL_HI_L 4

#define AGC2_VAL_HI (R_AGC2VAL2)|(AGC2_VAL_HI_S << 16)|(AGC2_VAL_HI_L << 24) 
/*  AGC2PGA */
#define R_AGC2PGA 0x1d 
/*#define F_AGC2PGA_RESERVED_1 77
#define UAGC2PGA 78  */

/*  OVF_RATE1   */
#define R_OVF_RATE1 0x1e
/*#define F_OVF_RESERVED_1 79
#define OVF_RATE_HI 80 */

/*  OVF_RATE2   */
#define R_OVF_RATE2 0x1f 
/*#define OVF_RATE_LO 81*/

/*  GAIN_SRC1   */
#define R_GAIN_SRC1 0x20 

#define INV_SPECTR_S 7
#define IQ_INVERT_S 6
#define INR_BYPASS_S 5 
#define GAIN_SRC_HI_S 0

#define INV_SPECTR_L 1
#define IQ_INVERT_L 1
#define INR_BYPASS_L 1 
#define GAIN_SRC_HI_L 4

#define INV_SPECTR (R_GAIN_SRC1)|(INV_SPECTR_S << 16)|(INV_SPECTR_L << 24)
#define IQ_INVERT (R_GAIN_SRC1)|(IQ_INVERT_S << 16)|(IQ_INVERT_L << 24)
#define INR_BYPASS (R_GAIN_SRC1)|(INR_BYPASS_S << 16)|(INR_BYPASS_L << 24)
#define GAIN_SRC_HI (R_GAIN_SRC1)|(GAIN_SRC_HI_S << 16)|(GAIN_SRC_HI_L << 24)
/*  GAIN_SRC2   */
#define R_GAIN_SRC2 0x21 
#define GAIN_SRC_LO_S 0
#define GAIN_SRC_LO_L 8

#define GAIN_SRC_LO (R_GAIN_SRC2)|(GAIN_SRC_LO_S << 16)|(GAIN_SRC_LO_L << 24)
/*  INC_DEROT1  */
#define R_INC_DEROT1 0x22 
/*#define INC_DEROT_HI 88 */

/*  INC_DEROT2  */
#define R_INC_DEROT2 0x23 
/*#define INC_DEROT_LO 89 */

/*  FREESTFE_1  */


#define R_FREESTFE_1 0x26 
/*#define F_FREESTFE_1_RESERVED_1 90
#define AVERAGE_ON 91
#define DC_ADJ 92
#define SEL_LSB 93 */

/*  SYR_THR  */
#define R_SYR_THR 0x27 
/*#define SEL_SRCOUT 94 
#define F_SYR_THR_RESERVED_1 95
#define SEL_SYRTHR 96*/

/* INR	*/
#define R_INR 0x28 
/*#define INR 97 */

/*  EN_PROCESS */
#define R_EN_PROCESS 0x29 
/*#define F_EN_PROCESS_RESERVED_1 98
#define ENAB 99*/

/* SDI_SMOOTHER */
#define R_SDI_SMOOTHER 0x2a 
/*#define DIS_SMOOTH 100 
#define F_SDI_SMOOTHER_RESERVED_1 101
#define SDI_INC_SMOOTHER 102*/

/* FE_LOOP_OPEN */
#define R_FE_LOOP_OPEN 0x2b 
/*#define F_FE_LOOP_OPEN_RESERVED_1 103
#define TRL_LOOP_OP 104
#define CRL_LOOP_OP 105 */

/* EPQ  */
#define R_EPQ 0x31 
 
#define EPQ_S 0

#define EPQ_L 8

#define EPQ (R_EPQ)|(EPQ_S << 16)|(EPQ_L << 24)

#define R_EPQ2 0x32 
/*#define EPQ2 107 */

/*  COR_CTL */
#define R_COR_CTL 0x80 
/*#define F_COR_CTL_RESERVED_1 108*/

#define CORE_ACTIVE_S 5
#define HOLD_S 4 
#define CORE_STATE_CTL_S 0 

#define CORE_ACTIVE_L 1
#define HOLD_L 1 
#define CORE_STATE_CTL_L 4

#define CORE_ACTIVE (R_COR_CTL)|(CORE_ACTIVE_S << 16)|(CORE_ACTIVE_L << 24) 
#define HOLD (R_COR_CTL)|(HOLD_S << 16)|(HOLD_L << 24)
#define CORE_STATE_CTL (R_COR_CTL)|(CORE_STATE_CTL_S << 16)|(CORE_STATE_CTL_L << 24)

/*  COR_STAT    */
#define R_COR_STAT 0x81 
/*#define F_COR_STAT_RESERVED_1 112*/

#define TPS_LOCKED_S 6
#define SYR_LOCKED_COR_S 5 
#define AGC_LOCKED_STAT_S 4 
#define CORE_STATE_STAT_S 0

 
#define TPS_LOCKED_L 1
#define SYR_LOCKED_COR_L 1 
#define AGC_LOCKED_STAT_L 1 
#define CORE_STATE_STAT_L 4

#define TPS_LOCKED (R_COR_STAT)|(TPS_LOCKED_S << 16)|(TPS_LOCKED_L << 24)
#define SYR_LOCKED_COR (R_COR_STAT)|(SYR_LOCKED_COR_S << 16)|(SYR_LOCKED_COR_L << 24)
#define AGC_LOCKED_STAT (R_COR_STAT)|(AGC_LOCKED_STAT_S << 16)|(AGC_LOCKED_STAT_L << 24)
#define CORE_STATE_STAT (R_COR_STAT)|(CORE_STATE_STAT_S << 16)|(CORE_STATE_STAT_L << 24) 
/*  COR_INTEN   */
#define R_COR_INTEN 0x82 
/*#define INTEN 117
#define F_COR_INTEN_RESERVED_1 118
#define INTEN_SYR 119
#define INTEN_FFT 120 
#define INTEN_AGC 121 
#define INTEN_TPS1 122 
#define INTEN_TPS2 123 
#define INTEN_TPS3 124 */

/*  COR_INTSTAT */
#define R_COR_INTSTAT 0x83 
/*#define F_COR_INTSTAT_RESERVED_1 125
#define INTSTAT_SYR 126
#define INTSTAT_FFT 127 
#define INTSAT_AGC 128
#define INTSTAT_TPS1 129 
#define INTSTAT_TPS2 130 
#define INTSTAT_TPS3 131 */

/*  COR_MODEGUARD   */
#define R_COR_MODEGUARD 0x84 
/*#define F_COR_MODEGUARD_RESERVED_1 132*/
#define FORCE_S 3
#define MODE_S 2 
#define GUARD_S 0
 
#define FORCE_L 1
#define MODE_L 1 
#define GUARD_L 2 

#define FORCE (R_COR_MODEGUARD)|(FORCE_S << 16)|(FORCE_L << 24)
#define MODE (R_COR_MODEGUARD)|(MODE_S << 16)|(MODE_L << 24)
#define GUARD (R_COR_MODEGUARD)|(GUARD_S << 16)|(GUARD_L << 24)
/*  AGC_CTL */
#define R_AGC_CTL 0x85 
/*#define DELAY_STARTUP 136
#define AGC_LAST 137
#define AGC_GAIN 138 
#define AGC_NEG 139
#define AGC_SET 140 */

/*  AGC_MANUAL1 */

#define R_AGC_MANUAL1 0x86 
/*#define AGC_VAL_LO 141 */

/*  AGC_MANUAL2 */

#define R_AGC_MANUAL2 0x87 
/*#define F_AGC_MANUAL2_RESERVED_1 142
#define AGC_VAL_HI 143*/

/*  AGC_TARGET  */
#define R_AGC_TARGET 0x88
/*#define AGC_TARGET 144 */

/*  AGC_GAIN1   */
#define R_AGC_GAIN1 0x89 
#define AGC_GAIN_LO_S 0

#define AGC_GAIN_LO_L 8

#define AGC_GAIN_LO (R_AGC_GAIN1)|(AGC_GAIN_LO_S << 16)|(AGC_GAIN_LO_L << 24)

/*  AGC_GAIN2   */
#define R_AGC_GAIN2 0x8a 
/*#define F_AGC_GAIN2_RESERVED_1 146*/
#define AGC_LOCKED_GAIN2_S 4
#define AGC_GAIN_HI_S 0
 
#define AGC_LOCKED_GAIN2_L 1
#define AGC_GAIN_HI_L 4 

#define AGC_LOCKED_GAIN2 (R_AGC_GAIN2)|(AGC_LOCKED_GAIN2_S << 16)|(AGC_LOCKED_GAIN2_L << 24)
#define AGC_GAIN_HI (R_AGC_GAIN2)|(AGC_GAIN_HI_S << 16)|(AGC_GAIN_HI_L << 24)

/*  ITB_CTL */
#define R_ITB_CTL 0x8b 
/*#define F_ITB_CTL_RESERVED_1 149
#define ITB_INVERT 150*/

/*  ITB_FREQ1   */
#define R_ITB_FREQ1 0x8c 
/*#define ITB_FREQ_LO 151 */

/*  ITB_FREQ2   */
#define R_ITB_FREQ2 0x8d
/*#define F_ITB_FREQ2_RESERVED_1 152
#define ITB_FREQ_HI 153 */

/*  CAS_CTL */
#define R_CAS_CTL 0x8e
/*#define CCS_ENABLE 154
#define ACS_DISABLE 155 
#define DAGC_DIS 156 
#define DAGC_GAIN 157 
#define CCSMU 158*/

/*  CAS_FREQ    */
#define R_CAS_FREQ 0x8f 
/*#define CCS_FREQ 159 */

/*  CAS_DAGCGAIN    */
#define R_CAS_DAGCGAIN 0x90 
/*#define CAS_DAGC_GAIN 160 */

/*  SYR_CTL */
#define R_SYR_CTL 0x91 

#define SICTHENABLE_S 7
#define LONG_ECHO_S 3 
#define AUTO_LE_EN_S 2 
#define SYR_BYPASS_S 1 
#define SYR_TR_DIS_S 0

 
#define SICTHENABLE_L 1
#define LONG_ECHO_L 4 
#define AUTO_LE_EN_L 1
#define SYR_BYPASS_L 1 
#define SYR_TR_DIS_L 1

#define SICTHENABLE (R_SYR_CTL)|(SICTHENABLE_S << 16)|(SICTHENABLE_L << 24)
#define LONG_ECHO (R_SYR_CTL)|(LONG_ECHO_S << 16)|(LONG_ECHO_L << 24)
#define AUTO_LE_EN (R_SYR_CTL)|(AUTO_LE_EN_S << 16)|(AUTO_LE_EN_L << 24)
#define SYR_BYPASS (R_SYR_CTL)|(SYR_BYPASS_S << 16)|(SYR_BYPASS_L << 24)
#define SYR_TR_DIS (R_SYR_CTL)|(SYR_TR_DIS_S << 16)|(SYR_TR_DIS_L << 24)


/*  SYR_STAT    */
#define R_SYR_STAT 0x92
/*#define F_SYR_STAT_RESERVED_1 166*/
#define SYR_LOCKED_STAT_S 4
#define SYR_MODE_S 2 
#define SYR_GUARD_S 0 

#define SYR_LOCKED_STAT_L 1
#define SYR_MODE_L 1 
#define SYR_GUARD_L 2 

#define SYR_LOCKED_STAT (R_SYR_STAT)|(SYR_LOCKED_STAT_S << 16)|(SYR_LOCKED_STAT_L << 24)
#define SYR_MODE (R_SYR_STAT)|(SYR_MODE_S << 16)|(SYR_MODE_L << 24)
#define SYR_GUARD (R_SYR_STAT)|(SYR_GUARD_S << 16)|(SYR_GUARD_L << 24)
/*  SYR_NCO1    */
#define R_SYR_NCO1 0x93 
/*#define SYR_NCO_LO 171 */

/*  SYR_NCO2    */
#define R_SYR_NCO2 0x94 
/*#define F_SYR_NCO2_RESERVED_1 172
#define SYR_NCO_HI 173*/

/*  SYR_OFFSET1 */
#define R_SYR_OFFSET1 0x95 
/*#define SYR_OFFSET_LO 174 */

/*  SYR_OFFSET2 */
#define R_SYR_OFFSET2 0x96 
/*#define F_SYR_OFFSET2_RESERVED_1 175
#define SYR_OFFSET_HI 176*/

/*  FFT_CTL */
#define R_FFT_CTL 0x97 
/*#define F_FFT_CTL_RESERVED_1 177
#define FFT_TRIGGER 178
#define FFT_MANUAL 179
#define IFFT_MODE 180*/

/*  SCR_CTL */
#define R_SCR_CTL 0x98 
/*#define F_SCR_CTL_RESERVED_1 181
#define SCR_CPDIS 182
#define SCR_DIS 183*/

/*  PPM_CTL1    */
#define R_PPM_CTL1 0x99 
/*#define F_PPM_CTL1_RESERVED_1 184
#define PPM_MAXFREQ 185 
#define F_PPM_CTL1_RESERVED_2 186
#define PPM_SCATDIS 187
#define PPM_BYP 188*/

/*  TRL_CTL */
#define R_TRL_CTL 0x9a 

#define TRL_NOMRATE_LSB_S 7
#define TRL_TR_GAIN_S 3
#define TRL_LOOPGAIN_S 0

 
#define TRL_NOMRATE_LSB_L 1
#define TRL_TR_GAIN_L 3
#define TRL_LOOPGAIN_L 1 

#define TRL_NOMRATE_LSB (R_TRL_CTL)|(TRL_NOMRATE_LSB_S << 16)|(TRL_NOMRATE_LSB_L << 24)
#define TRL_TR_GAIN (R_TRL_CTL)|(TRL_TR_GAIN_S << 16)|(TRL_TR_GAIN_L << 24)
#define TRL_LOOPGAIN (R_TRL_CTL)|(TRL_LOOPGAIN_S << 16)|(TRL_LOOPGAIN_L << 24)

/*  TRL_NOMRATE1    */
#define R_TRL_NOMRATE1 0x9b 

#define TRL_NOMRATE_LO_S 0 
#define TRL_NOMRATE_LO_L 8 

#define TRL_NOMRATE_LO (R_TRL_NOMRATE1)|(TRL_NOMRATE_LO_S << 16)|(TRL_NOMRATE_LO_L << 24)
/*  TRL_NOMRATE2    */
#define R_TRL_NOMRATE2 0x9c 

#define TRL_NOMRATE_HI_S 0 
#define TRL_NOMRATE_HI_L 8 

#define TRL_NOMRATE_HI (R_TRL_NOMRATE2)|(TRL_NOMRATE_HI_S << 16)|(TRL_NOMRATE_HI_L << 24)

/*  TRL_TIME1   */
#define R_TRL_TIME1 0x9d
 
#define TRL_TOFFSET_LO_S 0
#define TRL_TOFFSET_LO_L 8

#define TRL_TOFFSET_LO (R_TRL_TIME1)|(TRL_TOFFSET_LO_S << 16)|(TRL_TOFFSET_LO_L << 24)

/*  TRL_TIME2   */
#define R_TRL_TIME2 0x9e
 
#define TRL_TOFFSET_HI_S 0
#define TRL_TOFFSET_HI_L 8

#define TRL_TOFFSET_HI (R_TRL_TIME2)|(TRL_TOFFSET_HI_S << 16)|(TRL_TOFFSET_HI_L << 24)

/*  CRL_CTL */
#define R_CRL_CTL 0x9f 
/*#define CRL_DIS 197
#define F_CRL_CTL_RESERVED_1 198
#define CRL_TR_GAIN 199
#define CRL_LOOPGAIN 200 */

/*  CRL_FREQ1   */
#define R_CRL_FREQ1 0xa0
/*#define CRL_FOFFSET_LO 201 */

/*  CRL_FREQ2   */
#define R_CRL_FREQ2 0xa1 
/*#define CRL_FOFFSET_HI 202 */

/*  CRL_FREQ3   */
#define R_CRL_FREQ3 0xa2 
#define SEXT_S 7
#define CRL_FOFFSET_VHI_S 0

#define SEXT_L 1
#define CRL_FOFFSET_VHI_L 7

#define SEXT (R_CRL_FREQ3)|(SEXT_S << 16)|(SEXT_L << 24)
#define CRL_FOFFSET_VHI (R_CRL_FREQ3)|(CRL_FOFFSET_VHI_S << 16)|(CRL_FOFFSET_VHI_L << 24)
/*  CHC_CTL1    */
#define R_CHC_CTL1 0xa3
/*#define MEAN_PILOT_GAIN 205 
#define MMEANP 206
#define DBADP 207
#define DNOISEN 208 
#define DCHCPRED 209 
#define CHC_INT 210*/

/*  CHC_SNR */
#define R_CHC_SNR 0xa4 
 
#define CHC_SNR_S 0 
#define CHC_SNR_L 8 
#define CHC_SNR (R_CHC_SNR)|(CHC_SNR_S << 16)|(CHC_SNR_L << 24) 
/*  BDI_CTL */
#define R_BDI_CTL 0xa5 
/*#define F_BDI_CTL_RESERVED_1 212
#define BDI_LPSEL 213
#define BDI_SERIAL 214 */

/*  DMP_CTL */
#define R_DMP_CTL 0xa6
/*#define F_DMP_CTL_RESERVED_1 215
#define DMP_SDDIS 216*/

/*  TPS_RCVD1   */
#define R_TPS_RCVD1 0xa7 
/*#define F_TPS_RCVD1_RESERVED_1 217
#define TPS_CHANGE 218
#define BCH_OK 219
#define TPS_SYNC 220 
#define F_TPS_RCVD1_RESERVED_2 221
#define TPS_FRAME 222*/

/*  TPS_RCVD2   */
#define R_TPS_RCVD2 0xa8 
/*#define F_TPS_RCVD2_RESERVED_1 223*/
#define TPS_HIERMODE_S 4
#define TPS_CONST_S 0
#define TPS_HIERMODE_L 3
#define TPS_CONST_L 2

#define TPS_HIERMODE (R_TPS_RCVD2)|(TPS_HIERMODE_S << 16)|(TPS_HIERMODE_L << 24)
#define TPS_CONST (R_TPS_RCVD2)|(TPS_CONST_S << 16)|(TPS_CONST_L << 24)

/*  TPS_RCVD3   */
#define R_TPS_RCVD3 0xa9 
/*#define F_TPS_RCVD3_RESERVED_1 227*/
#define TPS_LPCODE_S 4
#define TPS_HPCODE_S 0

#define TPS_LPCODE_L 3
#define TPS_HPCODE_L 3

#define TPS_LPCODE (R_TPS_RCVD3)|(TPS_LPCODE_S << 16)|(TPS_LPCODE_L << 24)
#define TPS_HPCODE (R_TPS_RCVD3)|(TPS_HPCODE_S << 16)|(TPS_HPCODE_L << 24)

/*  TPS_RCVD4   */
#define R_TPS_RCVD4 0xaa
/*#define F_TPS_RCVD4_RESERVED_1  231*/

#define TPS_GUARD_S 4
/* #define F_TPS_RCVD4_RESERVED_2 233*/
#define TPS_MODE_S 0

#define TPS_GUARD_L 2
#define TPS_MODE_L 2

#define TPS_GUARD (R_TPS_RCVD4)|(TPS_GUARD_S << 16)|(TPS_GUARD_L << 24)
#define TPS_MODE (R_TPS_RCVD4)|(TPS_MODE_S << 16)|(TPS_MODE_L << 24)

/*  TPS_CELLID   */
#define R_TPS_CELLID 0xab 
 
#define TPS_CELLID_S 0
#define TPS_CELLID_L 8

#define TPS_CELLID (R_TPS_CELLID)|(TPS_CELLID_S << 16)|(TPS_CELLID_L << 24)

/*  TPS_FREE2   */
#define R_TPS_FREE2 0xac 

#define F_TPS_FREE2_RESERVED_1_S 0
#define F_TPS_FREE2_RESERVED_1_L 8

#define F_TPS_FREE2_RESERVED_1 (R_TPS_FREE2)|(F_TPS_FREE2_RESERVED_1_S << 16)|(F_TPS_FREE2_RESERVED_1_L << 24)

/*  TPS_SET1    */
#define R_TPS_SET1 0xad 
/*#define F_TPS_SET1_RESERVED_1 237*/
#define TPS_SETFRAME_S 0
#define TPS_SETFRAME_L 2

#define TPS_SETFRAME (R_TPS_SET1)|(TPS_SETFRAME_S << 16)|(TPS_SETFRAME_L << 24)

/*  TPS_SET2    */
#define R_TPS_SET2 0xae 
/*#define F_TPS_SET2_RESERVED_1 239
#define TPS_SETHIERMODE 240
#define F_TPS_SET2_RESERVED_2 241
#define TPS_SETCONST 242*/

/*  TPS_SET3    */
#define R_TPS_SET3 0xaf 
/*#define F_TPS_SET3_RESERVED_1 243
#define TPS_SETLPCODE 244
#define F_TPS_SET3_RESERVED_2 245
#define TPS_SETHPCODE 246*/

/*  TPS_CTL */
#define R_TPS_CTL 0xb0 
/*#define F_TPS_CTL_RESERVED_1 247
#define TPS_IMM 248
#define TPS_BCHDIS 249 
#define TPS_UPDDIS 250 */

/*  CTL_FFTOSNUM    */
#define R_CTL_FFTOSNUM 0xb1 
/*#define SYMBOL_NUMBER 251 */