360_map.h

st7710的tuner标准驱动

/* TSM_AP0 */
 #define R_TSM_AP0 0xb8
 #define ADDRESS_BYTE_0 0xb800ff

/* TSM_AP1 */
 #define R_TSM_AP1 0xb9
 #define ADDRESS_BYTE_1 0xb900ff

/* TSM_AP2 */
 #define R_TSM_AP2 0xba
 #define DATA_BYTE_0 0xba00ff

/* TSM_AP3 */
 #define R_TSM_AP3 0xbb
 #define DATA_BYTE_1 0xbb00ff

/* TSM_AP4 */
 #define R_TSM_AP4 0xbc
 #define DATA_BYTE_2 0xbc00ff

/* TSM_AP5 */
 #define R_TSM_AP5 0xbd
 #define DATA_BYTE_3 0xbd00ff

/* TSM_AP6 */
 #define R_TSM_AP6 0xbe



/* TSM_AP7 */
 #define R_TSM_AP7 0xbf
 #define MEM_SELECT_BYTE 0xbf00ff

/* CONSTMODE */
 #define R_CONSTMODE 0xcb
 #define CAR_TYPE 0xcb0018
 #define IQ_RANGE 0xcb0004
 #define CONST_MODE 0xcb0003


/* CONSTCARR1 */
 #define R_CONSTCARR1 0xcc
 #define CONST_CARR_LO 0xcc00ff

/* CONSTCARR2 */
 #define R_CONSTCARR2 0xcd
 #define CONST_CARR_HI 0xcd001f


/* ICONSTEL */
 #define R_ICONSTEL 0xce
 #define ICONSTEL 0xce01ff

/* QCONSTEL */
 #define R_QCONSTEL 0xcf
 #define QCONSTEL 0xcf01ff

/* AGC1RF */
 #define R_AGC1RF 0xd4
 #define RF_AGC1_LEVEL 0xd400ff

/* EN_RF_AGC1 */
 #define R_EN_RF_AGC1 0xd5
 #define START_ADC 0xd50080


/* FECM */
 #define R_FECM 0x40
 #define FEC_MODE 0x4000f0
 #define VIT_DIFF 0x400004
 #define SYNC 0x400002
 #define SYM 0x400001


/* VTH0 */
 #define R_VTH0 0x41
 #define VTH0 0x41007f


/* VTH1 */
 #define R_VTH1 0x42
 #define VTH1 0x42007f


/* VTH2 */
 #define R_VTH2 0x43
 #define VTH2 0x43007f


/* VTH3 */
 #define R_VTH3 0x44
 #define VTH3 0x44007f


/* VTH4 */
 #define R_VTH4 0x45
 #define VTH4 0x45007f


/* VTH5 */
 #define R_VTH5 0x46
 #define VTH5 0x46007f


/* FREEVIT */
 #define R_FREEVIT 0x47


/* VITPROG */
 #define R_VITPROG 0x49
 #define FORCE_ROTA 0x4900c0
 #define MDIVIDER 0x490003



/* PR */
 #define R_PR 0x4a
 #define FRAPTCR 0x4a0080
 #define E7_8 0x4a0020
 #define E6_7 0x4a0010
 #define E5_6 0x4a0008
 #define E3_4 0x4a0004
 #define E2_3 0x4a0002
 #define E1_2 0x4a0001


/* VSEARCH */
 #define R_VSEARCH 0x4b
 #define PR_AUTO 0x4b0080
 #define PR_FREEZE 0x4b0040
 #define SAMPNUM 0x4b0030
 #define TIMEOUT 0x4b000c
 #define HYSTER 0x4b0003

/* RS */
 #define R_RS 0x4c
 #define DEINT_ENA 0x4c0080
 #define OUTRS_SP 0x4c0040
 #define RS_ENA 0x4c0020
 #define DESCR_ENA 0x4c0010
 #define ERRBIT_ENA 0x4c0008
 #define FORCE47 0x4c0004
 #define CLK_POL 0x4c0002
 #define CLK_CFG 0x4c0001

/* RSOUT */
 #define R_RSOUT 0x4d
 #define ENA_STBACKEND 0x4d0010
 #define ENA8_LEVEL 0x4d000f

/* ERRCTRL1 */
 #define R_ERRCTRL1 0x4e
 #define ERRMODE1 0x4e0080
 #define TESTERS1 0x4e0040
 #define ERR_SOURCE1 0x4e0030
 #define RESET_CNTR1 0x4e0004
 #define NUM_EVENT1 0x4e0003


/* ERRCNTM1 */
 #define R_ERRCNTM1 0x4f
 #define ERROR_COUNT1_HI 0x4f00ff

/* ERRCNTL1 */
 #define R_ERRCNTL1 0x50
 #define ERROR_COUNT1_LO 0x5000ff

/* ERRCTRL2 */
 #define R_ERRCTRL2 0x51
 #define ERRMODE2 0x510080
 #define TESTERS2 0x510040
 #define ERR_SOURCE2 0x510030
 #define RESET_CNTR2 0x510004
 #define NUM_EVENT2 0x510003


/* ERRCNTM2 */
 #define R_ERRCNTM2 0x52
 #define ERROR_COUNT2_HI 0x5200ff

/* ERRCNTL2 */
 #define R_ERRCNTL2 0x53
 #define ERROR_COUNT2_LO 0x5300ff

/* ERRCTRL3 */
 #define R_ERRCTRL3 0x56
 #define ERRMODE3 0x560080
 #define TESTERS3 0x560040
 #define ERR_SOURCE3 0x560030
 #define RESET_CNTR3 0x560004
 #define NUM_EVENT3 0x560003


/* ERRCNTM3 */
 #define R_ERRCNTM3 0x57
 #define ERROR_COUNT3_HI 0x5700ff

/* ERRCNTL3 */
 #define R_ERRCNTL3 0x58
 #define ERROR_COUNT3_LO 0x5800ff

/* DILSTK1 */
 #define R_DILSTK1 0x59
 #define DILSTK_HI 0x5900ff


/* DILSTK0 */
 #define R_DILSTK0 0x5a
 #define DILSTK_LO 0x5a00ff


/* DILBWSTK1 */
 #define R_DILBWSTK1 0x5b

/* DILBWST0 */
 #define R_DILBWST0 0x5c





/* LNBRX */
 #define R_LNBRX 0x5d
 #define LINE_OK 0x5d0080
 #define OCCURRED_ERR 0x5d0040


/* RSTC */
 #define R_RSTC 0x5e
 #define DEINNTE 0x5e0080
 #define DIL64_ON 0x5e0040
 #define RSTC 0x5e0020
 #define DESCRAMTC 0x5e0010
 #define MODSYNCBYTE 0x5e0004
 #define LOWP_DIS 0x5e0002
 #define HI 0x5e0001



/* VIT_BIST */
 #define R_VIT_BIST 0x5f
 #define RAND_RAMP 0x5f0040
 #define NOISE_LEVEL 0x5f0038
 #define PR_VIT_BIST 0x5f0007


/* FREEDRS */
 #define R_FREEDRS 0x54


/* VERROR */
 #define R_VERROR 0x55
 #define ERROR_VALUE 0x5500ff

/* TSTRES */
 #define R_TSTRES 0xc0
 #define FRESI2C 0xc00080
 #define FRESRS 0xc00040
 #define FRESACS 0xc00020
 #define FRES_PRIF 0xc00010
 #define FRESFEC1_2 0xc00008
 #define FRESFEC 0xc00004
 #define FRESCORE1_2 0xc00002
 #define FRESCORE 0xc00001


/* ANACTRL */
 #define R_ANACTRL 0xc1
 #define STDBY_PLL 0xc10080
 #define BYPASS_XTAL 0xc10040
 #define STDBY_PGA 0xc10020
 #define TEST_PGA 0xc10010
 #define STDBY_ADC 0xc10008
 #define BYPASS_ADC 0xc10004
 #define SGN_ADC 0xc10002
 #define TEST_ADC 0xc10001


/* TSTBUS */
 #define R_TSTBUS 0xc2
 #define EXT_TESTIN 0xc20080
 #define EXT_ADC 0xc20040
 #define TEST_IN 0xc20038
 #define TS 0xc20007


/* TSTCK */
 #define R_TSTCK 0xc3
 #define CKFECEXT 0xc30080
 #define FORCERATE1 0xc30008
 #define TSTCKRS 0xc30004
 #define TSTCKDIL 0xc30002
 #define DIRCKINT 0xc30001



/* TSTI2C */
 #define R_TSTI2C 0xc4
 #define EN_VI2C 0xc40080
 #define TI2C 0xc40060
 #define BFAIL_BAD 0xc40010
 #define RBACT 0xc40008
 #define TST_PRIF 0xc40007


/* TSTRAM1 */
 #define R_TSTRAM1 0xc5
 #define SELADR1 0xc50080
 #define FSELRAM1 0xc50040
 #define FSELDEC 0xc50020
 #define FOEB 0xc5001c
 #define FADR 0xc50003

/* TSTRATE */
 #define R_TSTRATE 0xc6
 #define FORCEPHA 0xc60080
 #define FNEWPHA 0xc60010
 #define FROT90 0xc60008
 #define FR 0xc60007


/* SELOUT */
 #define R_SELOUT 0xc7
 #define EN_VLOG 0xc70080
 #define SELVIT60 0xc70040
 #define SELSYN3 0xc70020
 #define SELSYN2 0xc70010
 #define SELSYN1 0xc70008
 #define SELLIFO 0xc70004
 #define SELFIFO 0xc70002
 #define TSTFIFO_SELOUT 0xc70001

/* FORCEIN */
 #define R_FORCEIN 0xc8
 #define SEL_VITDATAIN 0xc80080
 #define FORCE_ACS 0xc80040
 #define TSTSYN 0xc80020
 #define TSTRAM64 0xc80010
 #define TSTRAM 0xc80008
 #define TSTERR2 0xc80004
 #define TSTERR 0xc80002
 #define TSTACS 0xc80001

/* TSTFIFO */
 #define R_TSTFIFO 0xc9
 #define FORMSB 0xc90004
 #define FORLSB 0xc90002
 #define TSTFIFO_TSTFIFO 0xc90001


/* TSTRS */
 #define R_TSTRS 0xca
 #define TST_SCRA 0xca0080
 #define OLDRS6 0xca0040
 #define ADCT 0xca0030
 #define DILT 0xca000c
 #define SCARBIT 0xca0002
 #define TSTRS_EN 0xca0001

/* TSTBISTRES0 */
 #define R_TSTBISTRES0 0xd0
 #define BEND_CHC2 0xd00080
 #define BBAD_CHC2 0xd00040
 #define BEND_PPM 0xd00020
 #define BBAD_PPM 0xd00010
 #define BEND_FFTW 0xd00008
 #define BBAD_FFTW 0xd00004
 #define BEND_FFTI 0xd00002
 #define BBAD_FFTI 0xd00001

/* TSTBISTRES1 */
 #define R_TSTBISTRES1 0xd1
 #define BEND_CHC1 0xd10080
 #define BBAD_CHC1 0xd10040
 #define BEND_SYR 0xd10020
 #define BBAD_SYR 0xd10010
 #define BEND_SDI 0xd10008
 #define BBAD_SDI 0xd10004
 #define BEND_BDI 0xd10002
 #define BBAD_BDI 0xd10001

/* TSTBISTRES2 */
 #define R_TSTBISTRES2 0xd2
 #define BEND_VIT2 0xd20080
 #define BBAD_VIT2 0xd20040
 #define BEND_VIT1 0xd20020
 #define BBAD_VIT1 0xd20010
 #define BEND_DIL 0xd20008
 #define BBAD_DIL 0xd20004
 #define BEND_RS 0xd20002
 #define BBAD_RS 0xd20001

/* TSTBISTRES3 */
 #define R_TSTBISTRES3 0xd3
 #define BEND_FIFO 0xd30002
 #define BBAD_FIFO 0xd30001


	/* Number of registers  */
/*#else     DEBUG_VERSION*/
#define		STV360_NBREGS	159

#define		STV360_NBFIELDS	466 

#else      /* Mini driver definitions*/

/*  ID  */
/*(RX123)||(FX_S << 8)|(FX_L << 12)*/
#define R_ID 0x00 
#define F_R_ID_S 0
#define F_R_ID_L 8
#define F_R_ID  (R_ID)|(F_R_ID_S << 16)|(F_R_ID_L << 24)
#define IDENTIFICATIONREGISTER 0 

/*  I2CRPT  */
#define R_I2CRPT 0x01 
#define I2CT_ON_S 7 
#define ENARPT_LEVEL_S 4 
#define SCLT_DELAY_S 3 
#define SCLT_NOD_S 2 
#define STOP_ENABLE_S 1 
#define F_I2CRPT_RESERVED_1_S 0

#define I2CT_ON_L 1 
#define ENARPT_LEVEL_L 3 
#define SCLT_DELAY_L 1 
#define SCLT_NOD_L 1 
#define STOP_ENABLE_L 1 
#define F_I2CRPT_RESERVED_1_L 1

#define I2CT_ON (R_I2CRPT)|(I2CT_ON_S << 16)|(I2CT_ON_L << 24) 
#define ENARPT_LEVEL (R_I2CRPT)|(ENARPT_LEVEL_S << 16)|(ENARPT_LEVEL_L << 24)
#define SCLT_DELAY (R_I2CRPT)|(SCLT_DELAY_S << 16)|(SCLT_DELAY_L << 24) 
#define SCLT_NOD (R_I2CRPT)|(SCLT_NOD_S << 16)|(SCLT_NOD_L << 24) 
#define STOP_ENABLE (R_I2CRPT)|(STOP_ENABLE_S << 16)|(STOP_ENABLE_L << 24) 
#define F_I2CRPT_RESERVED_1 (R_I2CRPT)|(F_I2CRPT_RESERVED_1_S << 16)|(F_I2CRPT_RESERVED_1_L << 24)

/*  TOPCTRL */
#define R_TOPCTRL 0x02 
#define STDBY_S 7 
#define STDBY_FEC_S 6 
#define STDBY_CORE_S 5 
#define DIR_CLK_S 4 
#define TS_DIS_S 3 
#define TQFP80_S 2 
#define BYPASS_PGA_S 1 
#define ENA_27_S 0 

#define STDBY_L 1 
#define STDBY_FEC_L 1 
#define STDBY_CORE_L 1 
#define DIR_CLK_L 1 
#define TS_DIS_L 1 
#define TQFP80_L 1 
#define BYPASS_PGA_L 1 
#define ENA_27_L 1 

#define STDBY (R_TOPCTRL)|(STDBY_S << 16)|(STDBY_L << 24) 
#define STDBY_FEC (R_TOPCTRL)|(STDBY_FEC_S << 16)|(STDBY_FEC_L << 24) 
#define STDBY_CORE (R_TOPCTRL)|(STDBY_CORE_S << 16)|(STDBY_CORE_L << 24) 
#define DIR_CLK (R_TOPCTRL)|(DIR_CLK_S << 16)|(DIR_CLK_L << 24) 
#define TS_DIS (R_TOPCTRL)|(TS_DIS_S << 16)|(TS_DIS_L << 24) 
#define TQFP80 (R_TOPCTRL)|(TQFP80_S << 16)|(TQFP80_L << 24) 
#define BYPASS_PGA (R_TOPCTRL)|(BYPASS_PGA_S << 16)|(BYPASS_PGA_L << 24) 
#define ENA_27 (R_TOPCTRL)|(ENA_27_S << 16)|(ENA_27_L << 24) 

/*  IOCFG0  */
#define R_IOCFG0 0x03 
/*#define OP0_SD 15 
#define OP0_VAL 16 
#define OP0_OD 17 
#define OP0_INV 18 
#define OP0_DACVALUE_HI 19 
*/
/*  DAC0R   */
#define R_DAC0R 0x04 
/*#define OP0_DACVALUE_LO 20 
*/
/*  IOCFG1  */
#define R_IOCFG1 0x05 
/*
#define F_IOCFG1_RESERVED_1 21
#define IP0 22 
#define OP1_OD 23 
#define OP1_INV 24 
#define OP1_DACVALUE_HI 25
*/
/*  DAC1R   */
#define R_DAC1R 0x06 
/*#define OP1_DACVALUE_LO 26 
*/
/*  IOCFG2  */
#define R_IOCFG2 0x07 
#define OP2_LOCK_CONF_S 5 
#define OP2_OD_S 4 
#define OP2_VAL_S 3 
#define OP1_LOCK_CONF_S 0 

#define OP2_LOCK_CONF_L 3 
#define OP2_OD_L 1 
#define OP2_VAL_L 1 
#define OP1_LOCK_CONF_L 3 

#define OP2_LOCK_CONF (R_IOCFG2)|(OP2_LOCK_CONF_S << 16)|(OP2_LOCK_CONF_L << 24) 
#define OP2_OD (R_IOCFG2)|(OP2_OD_S << 16)|(OP2_OD_L << 24) 
#define OP2_VAL (R_IOCFG2)|(OP2_VAL_S << 16)|(OP2_VAL_L << 24) 
#define OP1_LOCK_CONF (R_IOCFG2)|(OP1_LOCK_CONF_S << 16)|(OP1_LOCK_CONF_L << 24) 
/*  PWMFR    */
#define R_PWMFR 0x08 
/*#define OP0_FREQ 31 
#define OP1_FREQ 32 
*/
/*  STATUS  */
#define R_STATUS 0x09 
#define TPS_LOCK_S 7
#define SYR_LOCK_S 6 
#define AGC_LOCK_S 5 
#define PRF_S 4 
#define LK_S 3 
#define PR_S 0 

#define TPS_LOCK_L 1
#define SYR_LOCK_L 1 
#define AGC_LOCK_L 1 
#define PRF_L 1 
#define LK_L 1 
#define PR_L 3

#define TPS_LOCK (R_STATUS)|(TPS_LOCK_S << 16)|(TPS_LOCK_L << 24)
#define SYR_LOCK (R_STATUS)|(SYR_LOCK_S << 16)|(SYR_LOCK_L << 24)
#define AGC_LOCK (R_STATUS)|(AGC_LOCK_S << 16)|(AGC_LOCK_L << 24)
#define PRF (R_STATUS)|(PRF_S << 16)|(PRF_L << 24)
#define LK (R_STATUS)|(LK_S << 16)|(LK_L << 24)
#define PR (R_STATUS)|(PR_S << 16)|(PR_L << 24)
/*  AUX_CLK */
#define R_AUX_CLK 0x0a 
/*#define AUXFEC_ENA 40 
#define DIS_CKX4 41 
#define CKSEL 42 
#define CKDIV_PROG 43 
#define AUXCLK_ENA 44 
*/
/*  FREESYS1    */
#define R_FREESYS1 0x0b 
/*#define F_FREESYS1_RESERVED_1 45
*/
/*  FREESYS2    */
#define R_FREESYS2 0x0c 
/*#define F_FREESYS2_RESERVED_1 46
*/
/*  FREESYS3    */
#define R_FREESYS3 0x0d 
/*#define F_FREESYS3_RESERVED_1 47
*/
/*  AGC2MAX */
#define R_AGC2MAX 0x10 
/*#define AGC2MAX 48 
*/
/*  AGC2MIN */
#define R_AGC2MIN 0x11 
/*#define AGC2MIN 49
*/
/*  AGC1MAX */
#define R_AGC1MAX 0x12 
/*#define AGC1MAX 50 
*/
/*  AGC1MIN */
#define R_AGC1MIN 0x13 
/*#define AGC1MIN 51
*/
/*  AGCR    */
#define R_AGCR 0x14