d0372_map.h

st7710的tuner标准驱动

#ifndef H_D0372_MAP



	#define H_D0372_MAP



	#ifdef __cplusplus
	 extern "C"
	 {
	#endif                  /* __cplusplus */
	
#define		STV0372_NBREGS 165
#define 	STV0372_NBFIELDS 251	
	
/* ID */
 #define R0372_ID 0xf000
 #define F0372_IDENTIFICATIONREGISTER  0xf00000ff

/* I2C_PAGE */
 #define R0372_I2C_PAGE 0xf001
 #define F0372_REG_PAGE_ADRESS  0xf001000f

/* I2CRPT1 */
 #define R0372_I2CRPT1 0xf002
 #define F0372_I2CT_ON_1  0xf0020080
 #define F0372_ENARPT_LEVEL_1  0xf0020070
 #define F0372_SCLT_DELAY_1  0xf0020008
 #define F0372_SCLT_NOD_1  0xf0020004
 #define F0372_STOP_ENABLE_1  0xf0020002
 #define F0372_SDAT_NOD_1  0xf0020001

/* I2CRPT2 */
 #define R0372_I2CRPT2 0xf003
 #define F0372_I2CT_ON_2  0xf0030080
 #define F0372_ENARPT_LEVEL_2  0xf0030070
 #define F0372_SCLT_DELAY_2  0xf0030008
 #define F0372_SCLT_NOD_2  0xf0030004
 #define F0372_STOP_ENABLE_2  0xf0030002
 #define F0372_SDAT_NOD_2  0xf0030001

/* CLK_CTRL */
 #define R0372_CLK_CTRL 0xf004
 #define F0372_EN_EXTCLK_VSB  0xf0040040
 #define F0372_CLK50_VSBDEM  0xf0040004
 #define F0372_EN_CLKOSC  0xf0040002
 #define F0372_BYPASS_PLL  0xf0040001

/* STANDBY */
 #define R0372_STANDBY 0xf005
 #define F0372_STANDBY_AD10  0xf0050020
 #define F0372_STANDBY_VSB  0xf0050002

/* IO_CTRL */
 #define R0372_IO_CTRL 0xf006
 #define F0372_TS_HIGHZ  0xf0060080
 #define F0372_ACI_IO_NOD  0xf0060020
 #define F0372_AGC1_VSB_NOD  0xf0060010
 #define F0372_AGC2_VSB_NOD  0xf0060008

/* GPIO_INFO */
 #define R0372_GPIO_INFO 0xf007
 #define F0372_ACI_3PINS  0xf0070080
 #define F0372_SETINFO  0xf0070007

/* PLL_CTRL */
 #define R0372_PLL_CTRL 0xf610
 #define F0372_EN_CLKAD10  0xf6100080
 #define F0372_RFILT  0xf6100010
 #define F0372_SELICP  0xf6100008
 #define F0372_DIV  0xf6100004
 #define F0372_NOT_PWR_DN  0xf6100002
 #define F0372_NOT_RESET  0xf6100001

/* RESERVED */
 #define R0372_RESERVED 0xf611
 #define F0372_RESERVED  0xf61100ff

/* AD10_CTRL */
 #define R0372_AD10_CTRL 0xf61c
 #define F0372_INMODE  0xf61c0010
 #define F0372_ECO  0xf61c0008
 #define F0372_PWR_DN_MUX  0xf61c0004
 #define F0372_PWR_OFF_REF  0xf61c0002
 #define F0372_PWR_OFF  0xf61c0001

/* DEMOD_CTRL */
 #define R0372_DEMOD_CTRL 0xf010
 #define F0372_AGC_FREEZE  0xf0100080
 #define F0372_NCO_FREEZE  0xf0100040
 #define F0372_VCXO_FREEZE  0xf0100020
 #define F0372_A2DTYPE  0xf0100010
 #define F0372_INV_IQ  0xf0100004
 #define F0372_RST_TIMING  0xf0100002
 #define F0372_RST_CARRIER  0xf0100001

/* SYNCCTRL */
 #define R0372_SYNCCTRL 0xf011
 #define F0372_INVCNST  0xf0110002
 #define F0372_DCFREEZE  0xf0110001

/* AGCCTRL1 */
 #define R0372_AGCCTRL1 0xf012
 #define F0372_TAGCDIR  0xf0120040
 #define F0372_IAGCDIR  0xf0120020
 #define F0372_TST_PWM  0xf0120010
 #define F0372_INV_PWM  0xf0120008
 #define F0372_FRZAGCRF  0xf0120004
 #define F0372_FRZAGCIF  0xf0120002
 #define F0372_RSTAGC  0xf0120001

/* AGCCTRL2 */
 #define R0372_AGCCTRL2 0xf013
 #define F0372_ACCUMRSTSEL  0xf0130007

/* AGCPWR0372_LSB */
 #define R0372_AGCPWR_LSB 0xf014
 #define F0372_AGCPWR_LSB  0xf01400ff

/* AGCPWR0372_MSB */
 #define R0372_AGCPWR_MSB 0xf015
 #define F0372_AGCPWR_MSB  0xf0150003

/* AGCITHUP_LSB */
 #define R0372_AGCITHUP_LSB 0xf016
 #define F0372_AGCITHUP_LSB  0xf01600ff

/* AGCITHUP_MSB */
 #define R0372_AGCITHUP_MSB 0xf017
 #define F0372_AGCITHUP_MSB  0xf017000f

/* AGCITHLOW_LSB */
 #define R0372_AGCITHLOW_LSB 0xf018
 #define F0372_AGCITHLOW_LSB  0xf01800ff

/* AGCITHLOW_MSB */
 #define R0372_AGCITHLOW_MSB 0xf019
 #define F0372_AGCITHLOW_MSB  0xf019000f

/* AGCTH_LSB */
 #define R0372_AGCTH_LSB 0xf01a
 #define F0372_AGCTH_LSB  0xf01a00ff

/* AGCTH_MSB */
 #define R0372_AGCTH_MSB 0xf01b
 #define F0372_AGCTH_MSB  0xf01b000f

/* AGCBWSEL */
 #define R0372_AGCBWSEL 0xf01c
 #define F0372_AGCBWSEL  0xf01c000f

/* TAGCBWSEL */
 #define R0372_TAGCBWSEL 0xf01d
 #define F0372_TAGCBWSEL  0xf01d0007

/* TST_PWM1 */
 #define R0372_TST_PWM1 0xf01e
 #define F0372_PWMINRF_LSB  0xf01e00ff

/* TST_PWM2 */
 #define R0372_TST_PWM2 0xf01f
 #define F0372_PWMINIF_LSB  0xf01f00f0
 #define F0372_PWMINRF_MSB  0xf01f000f

/* TST_PWM3 */
 #define R0372_TST_PWM3 0xf020
 #define F0372_PWMINIF_MSB  0xf02000ff

/* AGC_IND_LSB */
 #define R0372_AGC_IND_LSB 0xf021
 #define F0372_AGC_IND_LSB  0xf02100ff

/* AGC_IND_MSB */
 #define R0372_AGC_IND_MSB 0xf022
 #define F0372_AGC_IND_MSB  0xf02200ff

/* AGC_IND_MMSB */
 #define R0372_AGC_IND_MMSB 0xf023
 #define F0372_AGC_IND_MMSB  0xf0230003

/* VCXOOFFSET1 */
 #define R0372_VCXOOFFSET1 0xf024
 #define F0372_VCXOOFFSET1  0xf02400ff

/* VCXOOFFSET2 */
 #define R0372_VCXOOFFSET2 0xf025
 #define F0372_VCXOOFFSET2  0xf02500ff

/* VCXOOFFSET3 */
 #define R0372_VCXOOFFSET3 0xf026
 #define F0372_VCXOOFFSET3  0xf02600ff

/* VCXOOFFSET4 */
 #define R0372_VCXOOFFSET4 0xf027
 #define F0372_VCXOOFFSET4  0xf027007f

/* GAINSRC_LSB */
 #define R0372_GAINSRC_LSB 0xf028
 #define F0372_GAINSRC_LSB  0xf02800ff

/* GAINSRC_MSB */
 #define R0372_GAINSRC_MSB 0xf029
 #define F0372_GAINSRC_MSB  0xf0290001

/* VCXOINITV */
 #define R0372_VCXOINITV 0xf02a
 #define F0372_VCXOINITV  0xf02a00ff

/* GAIN1ACQ1_LSB */
 #define R0372_GAIN1ACQ1_LSB 0xf02b
 #define F0372_GAIN1ACQ1_LSB  0xf02b00ff

/* GAIN1ACQ1_MSB */
 #define R0372_GAIN1ACQ1_MSB 0xf02c
 #define F0372_GAIN1ACQ1_MSB  0xf02c0003

/* GAIN1ACQ2_LSB */
 #define R0372_GAIN1ACQ2_LSB 0xf02d
 #define F0372_GAIN1ACQ2_LSB  0xf02d00ff

/* GAIN1ACQ2_MSB */
 #define R0372_GAIN1ACQ2_MSB 0xf02e
 #define F0372_GAIN1ACQ2_MSB  0xf02e0003

/* GAIN1TRACK_LSB */
 #define R0372_GAIN1TRACK_LSB 0xf02f
 #define F0372_GAIN1TRACK_LSB  0xf02f00ff

/* GAIN1TRACK_MSB */
 #define R0372_GAIN1TRACK_MSB 0xf030
 #define F0372_GAIN1TRACK_MSB  0xf0300003

/* GAIN2ACQ1_LSB */
 #define R0372_GAIN2ACQ1_LSB 0xf031
 #define F0372_GAIN2ACQ1_LSB  0xf03100ff

/* GAIN2ACQ1_MSB */
 #define R0372_GAIN2ACQ1_MSB 0xf032
 #define F0372_GAIN2ACQ1_MSB  0xf0320003

/* GAIN2ACQ2_LSB */
 #define R0372_GAIN2ACQ2_LSB 0xf033
 #define F0372_GAIN2ACQ2_LSB  0xf03300ff

/* GAIN2ACQ2_MSB */
 #define R0372_GAIN2ACQ2_MSB 0xf034
 #define F0372_GAIN2ACQ2_MSB  0xf0340003

/* GAIN2TRK_LSB */
 #define R0372_GAIN2TRK_LSB 0xf035
 #define F0372_GAIN2TRK_LSB  0xf03500ff

/* GAIN2TRK_MSB */
 #define R0372_GAIN2TRK_MSB 0xf036
 #define F0372_GAIN2TRK_MSB  0xf0360003

/* GAIN3ACQ */
 #define R0372_GAIN3ACQ 0xf037
 #define F0372_GAIN3ACQ  0xf03700ff

/* GAIN3TRK */
 #define R0372_GAIN3TRK 0xf038
 #define F0372_GAIN3TRK  0xf03800ff

/* VCXOERR0372_LSB */
 #define R0372_VCXOERR_LSB 0xf039
 #define F0372_VCXO_ERR_LSB  0xf03900ff

/* VCXOERR0372_MSB */
 #define R0372_VCXOERR_MSB 0xf03a
 #define F0372_VCXOERR_MSB  0xf03a00ff

/* VCXOERR0372_MMSB */
 #define R0372_VCXOERR_MMSB 0xf03b
 #define F0372_VCXOERR_MMSB  0xf03b00ff

/* TIMLOCKDETECT_LSB */
 #define R0372_TIMLOCKDETECT_LSB 0xf03c
 #define F0372_TIMLOCKDETECT_LSB  0xf03c00ff

/* TIMLOCKDETECT_MSB */
 #define R0372_TIMLOCKDETECT_MSB 0xf03d
 #define F0372_TIMLOCKDETECT_MSB  0xf03d00ff

/* TIMLOCKDETECT_MMSB */
 #define R0372_TIMLOCKDETECT_MMSB 0xf03e
 #define F0372_FREQ_LOCK  0xf03e0004
 #define F0372_TIMLOCKDETECT_MMSB  0xf03e0003

/* FREQLOCK_LSB */
 #define R0372_FREQLOCK_LSB 0xf03f
 #define F0372_FREQLOCKTH_LSB  0xf03f00ff

/* FREQLOCK_MSB */
 #define R0372_FREQLOCK_MSB 0xf040
 #define F0372_FREQLOCKTH_MSB  0xf04000ff

/* FREQLOCK_MMSB */
 #define R0372_FREQLOCK_MMSB 0xf041
 #define F0372_FREQLOCKTH_MMSB  0xf0410003

/* TIMINGAGCREF_LSB */
 #define R0372_TIMINGAGCREF_LSB 0xf042
 #define F0372_TIMINGAGCREF_LSB  0xf04200ff

/* TIMINGAGCREF_MSB */
 #define R0372_TIMINGAGCREF_MSB 0xf043
 #define F0372_TIMINGAGCREF_MSB  0xf043000f

/* NCOCNST_LSB */
 #define R0372_NCOCNST_LSB 0xf044
 #define F0372_NCOCNST_LSB  0xf04400ff

/* NCOCNST_MSB */
 #define R0372_NCOCNST_MSB 0xf045
 #define F0372_NCOCNST_MSB  0xf04500ff

/* NCOCNST_MMSB */
 #define R0372_NCOCNST_MMSB 0xf046
 #define F0372_NCOCNST_MMSB  0xf046007f

/* NCOGAIN1ACQ */
 #define R0372_NCOGAIN1ACQ 0xf047
 #define F0372_NCOGAIN1ACQ  0xf04700ff

/* NCOGAIN1TRACK */
 #define R0372_NCOGAIN1TRACK 0xf048
 #define F0372_NCOGAIN1TRACK  0xf04800ff

/* NCOGAIN2ACQ */
 #define R0372_NCOGAIN2ACQ 0xf049
 #define F0372_NCOGAIN2ACQ  0xf04900ff

/* NCOGAIN2TRACK */
 #define R0372_NCOGAIN2TRACK 0xf04a
 #define F0372_NCOGAIN2TRACK  0xf04a00ff

/* NCOGAIN3 */
 #define R0372_NCOGAIN3 0xf04b
 #define F0372_NCOGAIN3  0xf04b00ff

/* NCOERR_LSB */
 #define R0372_NCOERR_LSB 0xf04c
 #define F0372_NCOERR_LSB  0xf04c00ff

/* NCOERR_MSB */
 #define R0372_NCOERR_MSB 0xf04d
 #define F0372_NCOERR_MSB  0xf04d00ff

/* NCOERR_MMSB */
 #define R0372_NCOERR_MMSB 0xf04e
 #define F0372_NCOERR_MMSB  0xf04e0001

/* CARLOCKDETECT1_LSB */
 #define R0372_CARLOCKDETECT1_LSB 0xf04f
 #define F0372_CARLOCKDETECT1_LSB  0xf04f00ff

/* CARLOCKDETECT1_MSB */
 #define R0372_CARLOCKDETECT1_MSB 0xf050
 #define F0372_CARLOCKDETECT1_MSB  0xf05000ff

/* CARLOCKDETECT1_MMSB */
 #define R0372_CARLOCKDETECT1_MMSB 0xf051
 #define F0372_CY_LOCK  0xf0510004
 #define F0372_CARLOCKDETECT1_MMSB  0xf0510003

/* CARLOCKDETECT2_LSB */
 #define R0372_CARLOCKDETECT2_LSB 0xf052
 #define F0372_CARLOCKDETECT2_LSB  0xf05200ff

/* CARLOCKDETECT2_MSB */
 #define R0372_CARLOCKDETECT2_MSB 0xf053
 #define F0372_CARLOCKDETECT2_MSB  0xf05300ff

/* CARLOCKDETECT2_MMSB */
 #define R0372_CARLOCKDETECT2_MMSB 0xf054
 #define F0372_CARLOCKDETECT2_MMSB  0xf0540003

/* CARRIERLOCKTH_LSB */
 #define R0372_CARRIERLOCKTH_LSB 0xf055
 #define F0372_CARRIERLOCKTH_LSB  0xf05500ff

/* CARRIERLOCKTH_MSB */
 #define R0372_CARRIERLOCKTH_MSB 0xf056