gpiflongxfr.c

FX2开发板程序下载C

BOOL DR_GetStatus( void )
{
   return( TRUE );
}

BOOL DR_ClearFeature( void )
{
   return( TRUE );
}

BOOL DR_SetFeature( void )
{
   return( TRUE );
}

#define VX_B2 0xB2              // turn OFF debug LEDs...
#define VX_B4 0xB4              // read GPIFTRIG register
#define VX_B5 0xB5              // GPIFABORT
#define VX_B7 0xB7              // re-initialize, call TD_Init( );
#define VX_B8 0xB8              // do a "soft reset", vector to org 00h
#define VX_B9 0xB9              // commit IN pkt. via INPKTEND=6
#define VX_C0 0xC0              // td poll handles data transfers
#define VX_C1 0xC1              // vend cmnd handles data transfers
#define VX_C2 0xC2              // cpu source out data
#define VX_C3 0xC3              // switch to AUTOOUT=1, auto mode
#define VX_C4 0xC4              // switch to AUTOOUT=0, manual mode
#define VX_C5 0xC5              // read REVCTL register
#define VX_D0 0xD0              // read GPIFTCx registers
#define VX_D1 0xD1              // setup GPIFTCx = 0xFFFFFFFF;
#define VX_D2 0xD2              // launch GPIF FIFOWr Waveform


// Core uses bRequest value 0xA0 for Anchor downloads/uploads...
// Cypress Semiconductor reserves bRequest values 0xA1 through 0xAF...
// Your implementation should not use the above bRequest values...
// Also, previous fw.c versions trap all bRequest values 0x00 through 0x0F...
//
//   bRequest value: SETUPDAT[1]
//   standard, 0x00 through 0x0F
//
//   bmRequest value: SETUPDAT[0]
//   standard,  0x80 IN   Token
//   vendor,    0xC0 IN   Token
//   class,     0xA0 IN   Token
//   standard,  0x00 OUT  Token
//   vendor,    0x40 OUT  Token
//   class,     0x60 OUT  Token

BOOL DR_VendorCmnd( void )
{
  
  // Registers which require a synchronization delay, see section 15.14
  // FIFORESET        FIFOPINPOLAR
  // INPKTEND         OUTPKTEND
  // EPxBCH:L         REVCTL
  // GPIFTCB3         GPIFTCB2
  // GPIFTCB1         GPIFTCB0
  // EPxFIFOPFH:L     EPxAUTOINLENH:L
  // EPxFIFOCFG       EPxGPIFFLGSEL
  // PINFLAGSxx       EPxFIFOIRQ
  // EPxFIFOIE        GPIFIRQ
  // GPIFIE           GPIFADRH:L
  // UDMACRCH:L       EPxGPIFTRIG
  // GPIFTRIG
  
  // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
  //      ...these have been replaced by GPIFTC[B3:B0] registers

	switch( SETUPDAT[ 1 ] )
	{ 
    case VX_B2:
    { // turn OFF debug LEDs...
    
      ledX_rdvar = LED0_OFF;    // visual
      ledX_rdvar = LED1_OFF;    // visual
      ledX_rdvar = LED2_OFF;    // visual
      ledX_rdvar = LED3_OFF;    // visual
      
      *EP0BUF = VX_B2;
      break;
    }
    case VX_B4:
    { 
      *EP0BUF = GPIFTRIG;
      break;
    }
    case VX_B5:
    { 
      GPIFABORT = 0xFF;
      *EP0BUF = VX_B5;
      break;
    }
    case VX_B7:
    { 
      TD_Init( );
      *EP0BUF = VX_B7;
      break;
    }
    case VX_B8:
    { 
      EP0BCH = 0;
      EP0BCL = 1;                   // Arm endpoint with # bytes to transfer
      EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
      SYNCDELAY;                    // used here as "delay"
      SYNCDELAY;                    // used here as "delay"
      
      EA = 0;             
                      
      // ...do a "soft" code only RESET... vector to ORG 0x0000
      ( ( void ( code * ) ( void ) ) 0x0000 ) ( );
      
      *EP0BUF = VX_B8;
      break;
    }
    case VX_B9:
    { 
      // AUTOIN=0, so 8051 pass pkt. to host...
      SYNCDELAY;                // 
      INPKTEND = 0x06;          // ...w/skip=0; commit however many bytes in pkt.
      SYNCDELAY;                // 
                                // ...NOTE: this also handles "shortpkt"
      *EP0BUF = VX_B9;
      break;
    }
    case VX_C0:
    { // td_poll(); handles data transfers
      td_poll_handles_transfers = 1;
      *EP0BUF = VX_C0;
      break;
    }
    case VX_C1:
    { // vend cmnds handle data transfers
      td_poll_handles_transfers = 0;
      *EP0BUF = VX_C1;
      break;
    }
    case VX_C2:
    { // cpu source out data
      if( EP24FIFOFLGS & 0x02 )
      {
        REVCTL = 0x01;            // ENH_PKT=1 (enabled in TD_Init( ); as well...)
        SYNCDELAY;                // 
        FIFORESET = 0x80;         // nak all OUT pkts. from host
        SYNCDELAY;                // 
        FIFORESET = 0x02;         // advance all EP2 buffers to cpu domain
        SYNCDELAY;                // 
        EP2FIFOBUF[0] = 0xAA;     // create newly source pkt. data
        SYNCDELAY;                // 
        EP2BCH = 0x00;
        SYNCDELAY;                // 
        EP2BCL = 0x01;            // commit newly sourced pkt. to interface fifo
      
        // setup GPIF transaction count
        SYNCDELAY;
        GPIFTCB3 = 0x00;
        SYNCDELAY;
        GPIFTCB2 = 0x00;
        SYNCDELAY;
        GPIFTCB1 = 0x00;
        SYNCDELAY;
        GPIFTCB0 = 0x01;
      
        // trigger FIFO write transaction(s), using SFR
        // R/W=0, EP[1:0]=00 for EP2 write(s)
        SYNCDELAY;
        GPIFTRIG = GPIFTRIGWR | GPIF_EP2;  
      
        // one byte (value = 0xAA) transfers over the peripheral bus
        SYNCDELAY;
        // wait for the transaction to terminate naturally...
        while( !( GPIFTRIG & 0x80 ) )
        { 
          ; // poll GPIFTRIG.7, DONE bit...
        }
      
        // beware of "left over" uncommitted buffers
                                
        SYNCDELAY;                // 
        OUTPKTEND = 0x82;         // skip uncommitted pkt. (second pkt.)
        SYNCDELAY;                // 
        OUTPKTEND = 0x82;         // skip uncommitted pkt. (third pkt.)
        SYNCDELAY;                // 
        OUTPKTEND = 0x82;         // skip uncommitted pkt. (fourth pkt.)
        // note: core will not allow pkts. to get out of sequence
        SYNCDELAY;                // 
        FIFORESET = 0x00;         // release "nak all"
        SYNCDELAY;
      
        *EP0BUF = VX_C2;
      }
      else
      {
        *EP0BUF = 0xFF;
      }
      
      break;
    }
    case VX_C3:
    { // switch to AUTO mode
      SYNCDELAY;                // 
      EP2FIFOCFG = 0x10;        // AUTOOUT=1
      SYNCDELAY;                // 
      EP6FIFOCFG = 0x05;        // AUTOIN=1
      // NOTE: these can be performed independently
      endp_auto_mode_enabled = 1;
      *EP0BUF = VX_C3;
      break;
    }
    case VX_C4:
    { // switch to MANUAL mode
      SYNCDELAY;                // 
      EP2FIFOCFG = 0x00;        // AUTOOUT=0
      SYNCDELAY;                // 
      EP6FIFOCFG = 0x04;        // AUTOIN=0
      // NOTE: these can be performed independently
      endp_auto_mode_enabled = 0;
      *EP0BUF = VX_C4;
      break;
    }
    case VX_C5:
    { // read REVCTL register
      *EP0BUF = REVCTL;
      break;
    }
    case VX_D0:
    { // read live GPIF Transaction Count
      EP0BUF[0] = GPIFTCB3;
      EP0BUF[1] = GPIFTCB2;
      EP0BUF[2] = GPIFTCB1;
      EP0BUF[3] = GPIFTCB0;
      EP0BUF[4] = VX_D0;
      EP0BCH = 0;
      EP0BCL = 5;                   // Arm endpoint with # bytes to transfer
      EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
  
	    return( FALSE );              // no error; command handled OK
      break;
    }
    case VX_D1:
    { // setup GPIF transaction count
      
      GPIFTCB3 = 0xFF;
      SYNCDELAY;                    // 
      GPIFTCB2 = 0xFF;
      SYNCDELAY;                    // 
      GPIFTCB1 = 0xFF;
      SYNCDELAY;                    // 
      GPIFTCB0 = 0xFF;
      SYNCDELAY;                    // 
      
      *EP0BUF = VX_D1;
      break;
    }
    case VX_D2:
    { 
      // you may wish to check your peripheral's status here...
      
      // trigger FIFO write transaction(s), using SFR
      // R/W=0, EP[1:0]=00 for EP2 write(s)
      SYNCDELAY;                    // 
      GPIFTRIG = GPIFTRIGWR | GPIF_EP2;  
      
      // NOTE: 512 bytes transfers in ~75usec on 8-bit async bus 
      // ...once master (GPIF) drains OUT pkt, it (re)arms to usb domain
      *EP0BUF = VX_D2;
      break;
    }
    default:
    {
      ledX_rdvar = LED3_ON;     // debug visual, stuck "ON" to warn developer...
	    return( FALSE );          // no error; command handled OK
    }
	}
  
  EP0BCH = 0;
  EP0BCL = 1;                   // Arm endpoint with # bytes to transfer
  EP0CS |= bmHSNAK;             // Acknowledge handshake phase of device request
  
	return( FALSE );              // no error; command handled OK
}

//-----------------------------------------------------------------------------
// USB Interrupt Handlers
//   The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------

// Setup Data Available Interrupt Handler
void ISR_Sudav( void ) interrupt 0
{
   GotSUD = TRUE;         // Set flag
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUDAV;      // Clear SUDAV IRQ
}

// Setup Token Interrupt Handler
void ISR_Sutok( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUTOK;      // Clear SUTOK IRQ
}

void ISR_Sof( void ) interrupt 0
{
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSOF;        // Clear SOF IRQ
}

void ISR_Ures( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }
   
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmURES;       // Clear URES IRQ
}

void ISR_Susp( void ) interrupt 0
{
   Sleep = TRUE;
   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmSUSP;
}

void ISR_Highspeed( void ) interrupt 0
{
   if ( EZUSB_HIGHSPEED( ) )
   {
      pConfigDscr = pHighSpeedConfigDscr;
      pOtherConfigDscr = pFullSpeedConfigDscr;
   }
   else
   {
      pConfigDscr = pFullSpeedConfigDscr;
      pOtherConfigDscr = pHighSpeedConfigDscr;
   }

   EZUSB_IRQ_CLEAR( );
   USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack( void ) interrupt 0
{
}
void ISR_Stub( void ) interrupt 0
{
}
void ISR_Ep0in( void ) interrupt 0
{
}
void ISR_Ep0out( void ) interrupt 0
{
}
void ISR_Ep1in( void ) interrupt 0
{
}
void ISR_Ep1out( void ) interrupt 0
{
}
void ISR_Ep2inout( void ) interrupt 0
{
}
void ISR_Ep4inout( void ) interrupt 0
{
}
void ISR_Ep6inout( void ) interrupt 0
{
}
void ISR_Ep8inout( void ) interrupt 0
{
}
void ISR_Ibn( void ) interrupt 0
{
}
void ISR_Ep0pingnak( void ) interrupt 0
{
}
void ISR_Ep1pingnak( void ) interrupt 0
{
}
void ISR_Ep2pingnak( void ) interrupt 0
{
}
void ISR_Ep4pingnak( void ) interrupt 0
{
}
void ISR_Ep6pingnak( void ) interrupt 0
{
}
void ISR_Ep8pingnak( void ) interrupt 0
{
}
void ISR_Errorlimit( void ) interrupt 0
{
}
void ISR_Ep2piderror( void ) interrupt 0
{
}
void ISR_Ep4piderror( void ) interrupt 0
{
}
void ISR_Ep6piderror( void ) interrupt 0
{
}
void ISR_Ep8piderror( void ) interrupt 0
{
}
void ISR_Ep2pflag( void ) interrupt 0
{
}
void ISR_Ep4pflag( void ) interrupt 0
{
}
void ISR_Ep6pflag( void ) interrupt 0
{
}
void ISR_Ep8pflag( void ) interrupt 0
{
}
void ISR_Ep2eflag( void ) interrupt 0
{
}
void ISR_Ep4eflag( void ) interrupt 0
{
}
void ISR_Ep6eflag( void ) interrupt 0
{
}
void ISR_Ep8eflag( void ) interrupt 0
{
}
void ISR_Ep2fflag( void ) interrupt 0
{
}
void ISR_Ep4fflag( void ) interrupt 0
{
}
void ISR_Ep6fflag( void ) interrupt 0
{
}
void ISR_Ep8fflag( void ) interrupt 0
{
}
void ISR_GpifComplete( void ) interrupt 0
{
}
void ISR_GpifWaveform( void ) interrupt 0
{  // FIFORd WF detected peripheral prematurely empty (less than max. pkt. size)

  GPIFABORT = 0xFF;             // abort to handle shortpkt
  
  SYNCDELAY;
	EXIF &=  ~0x40;
  INT4CLR = 0xFF;             // automatically enabled at POR
  SYNCDELAY;
}