ltcrt.c

此代码为WCE5.0下显示器的源代码

/******************************Public*Routine********************************\
* VOID CRTPostModeChange(HGDO hGDO,
*                 LPDEVMODE_INFO lpMI)
* GDOPostModeChange performs any post-mode configuration or cleanup
* required by the display after a mode change occurs.
*
\****************************************************************************/
VOID FAR
CRTPostModeChange(HGDO hGDO,
  LPDEVMODE_INFO lpMI
  )
{
    LPGDO_RAGE_CRT  hGDORageCRT;
    ULONG           ulTotal_Disp_Data;
    ULONG           ulSync_Strt_Wid_Data;
    ULONG           ulSync_Start_Hi;
    ULONG           ulOverScan_Data;
    ULONG           ulCRTCExtCntl_data;

    hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;

    DALDEBUG((DALDBG_NORMAL, "ATIRAGE.SYS! GDO-CRT: CRTSetMode - Entry"));

    //
    // Set up default values for Horizontal and Vertical informations.
    //

    // For LT Rage Pro, we need to select controller for CRTC register R/W.
    if ( hGDORageCRT->ulChipFamily == FAMILY_LT_PRO ||
         hGDORageCRT->ulChipFamily == FAMILY_RAGE_MOBILITY )
        SelectCRTCRW(hGDO);

    //
    // fill in Horizontal information
    //
    ulTotal_Disp_Data = MMREADULONG(hGDORageCRT->lpMMR, CRTC_H_TOTAL_DISP);

    hGDORageCRT->ulHTotal = (ulTotal_Disp_Data &
                                      CRTC_H_TOTAL_DISP__CRTC_H_TOTAL_MASK);
    hGDORageCRT->ulHDispEnd = ((ulTotal_Disp_Data &
                                    CRTC_H_TOTAL_DISP__CRTC_H_DISP_MASK)>>16);

    ulSync_Strt_Wid_Data = MMREADULONG(hGDORageCRT->lpMMR,
                                        CRTC_H_SYNC_STRT_WID);

    hGDORageCRT->ulPreviousHSyncStart =
    hGDORageCRT->ulInitialHSyncStart =
    hGDORageCRT->ulHSyncStart = ((ulSync_Strt_Wid_Data &
                        CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_MASK));

    ulSync_Start_Hi = (ulSync_Strt_Wid_Data &
                           CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_HI_MASK);

    hGDORageCRT->ulInitialHSyncStart |= (ulSync_Start_Hi >> 4);

    hGDORageCRT->ulHSyncWidth = ((ulSync_Strt_Wid_Data &
                             CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_WID_MASK)>>16);

    hGDORageCRT->ucHorizontalSync = (UCHAR)((ulSync_Strt_Wid_Data &
                             CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_POL)>> 21);

    ulOverScan_Data = MMREADULONG(hGDORageCRT->lpMMR, OVR_WID_LEFT_RIGHT);

    hGDORageCRT->ulLeftOverScan = (ulOverScan_Data &
                           OVR_WID_LEFT_RIGHT__OVR_WID_LEFT_MASK);

    hGDORageCRT->ulRightOverScan = ((ulOverScan_Data &
                             OVR_WID_LEFT_RIGHT__OVR_WID_RIGHT_MASK)>>16);
    //
    // fill in the Vertical information
    //
    ulTotal_Disp_Data = MMREADULONG(hGDORageCRT->lpMMR, CRTC_V_TOTAL_DISP);

    hGDORageCRT->ulVTotal = (ulTotal_Disp_Data &
                                      CRTC_V_TOTAL_DISP__CRTC_V_TOTAL_MASK);
    hGDORageCRT->ulVDispEnd =((ulTotal_Disp_Data &
                                    CRTC_V_TOTAL_DISP__CRTC_V_DISP_MASK)>>16);

    ulSync_Strt_Wid_Data = MMREADULONG(hGDORageCRT->lpMMR,
                                        CRTC_V_SYNC_STRT_WID);

    hGDORageCRT->ulPreviousVSyncStart =
    hGDORageCRT->ulInitialVSyncStart =
    hGDORageCRT->ulVSyncStart = ((ulSync_Strt_Wid_Data &
                        CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_STRT_MASK));

    hGDORageCRT->ulVSyncWidth = ((ulSync_Strt_Wid_Data &
                             CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_WID_MASK)>>16);

    hGDORageCRT->ucVerticalSync = (UCHAR)((ulSync_Strt_Wid_Data &
                             CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_POL)>> 21);

    ulOverScan_Data = MMREADULONG(hGDORageCRT->lpMMR, OVR_WID_TOP_BOTTOM);

    hGDORageCRT->ulTopOverScan = (ulOverScan_Data &
                                  OVR_WID_TOP_BOTTOM__OVR_WID_TOP_MASK);

    hGDORageCRT->ulBottomOverScan = ((ulOverScan_Data &
                                OVR_WID_TOP_BOTTOM__OVR_WID_BOTTOM_MASK)>>16);

    //
    // fill in the current composite syn data
    //
    // Read Gen Ctrl data
    ulCRTCExtCntl_data = MMREADULONG(hGDORageCRT->lpMMR, CRTC_GEN_CNTL);

    hGDORageCRT->ucCompositeSync =(UCHAR)
                ((ulCRTCExtCntl_data & CRTC_GEN_CNTL__CRTC_CSYNC_EN)>>4);

    // For LT Rage Pro, we need to restore CRTC register R/W back to 0.
    if ( hGDORageCRT->ulChipFamily == FAMILY_LT_PRO ||
         hGDORageCRT->ulChipFamily == FAMILY_RAGE_MOBILITY )
        RestoreCRTCRW(hGDO);

} // end CRTPostModeChange

/******************************Public*Routine******************************\
*VOID CRTSetDPMS(HW_DISPLAY_OBJ hGDO, ULONG ulstate)
*
* CRTSetDPMS is used to set the display power management state.
*
* ulstate specifies the display power management state, as one of
* DPMS_ACTIVE, DPMS_STANDBY, DPMS_SUSPEND, and DPMS_OFF.
*
* The settings are:
* DPMS_ACTIVE: Everything on.
* DPMS_STANDBY: Disable Disable H_Sync
* DPMS_SUSPEND: Disable Disable V_Sync
* DPMS_OFF    : Disable H_Sync and V_Sync
*
\**************************************************************************/
VOID FAR
CRTSetDPMS(
    HGDO hGDO,
    ULONG ulState
    )
{
    ULONG               ulLCDIndex;
    ULONG               ulLCDGenCtrlData;
    ULONG               ulCRTCExtCntl_data;
    ULONG               ulDacCntlData;  
    LPGDO_RAGE_CRT      hGDORageCRT;

    hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;

    DALDEBUG((DALDBG_NORMAL, "ATIRAGE.SYS! GDO-CRT: CRTSetDPMS - Entry"));


    // No LCD data register for RAGE PRO family
    if(hGDORageCRT->ulChipFamily == FAMILY_GTC) // EPR# 042986 Task# 5994
    {
       // EPR#51282, Task#8039
       ulDacCntlData = MMREADULONG(hGDORageCRT->lpMMR, DAC_CNTL);
       switch(ulState)
       {
         case(POWERSTATE_ON):

           // set DAC_PDWN to 0 which turns on the CRT display.
           ulDacCntlData &= ~DAC_CNTL__DAC_PDWN; 
           break;

         case(POWERSTATE_STANDBY):

         case(POWERSTATE_SUSPEND):

         case(POWERSTATE_OFF):

           // set DAC_PDWN bit to 1 which turns off the CRT display.
           ulDacCntlData |= DAC_CNTL__DAC_PDWN; 
           break; 
       }// end switch

       MMWRITEULONG(hGDORageCRT->lpMMR, DAC_CNTL, ulDacCntlData);
       return;
    }
    //EPR#039657 twdal#4681 Fn+F3 do not turn off CRT on secondary in W2K

    // Set LCD_DATA register to index 1( LCD_GEN_CTRL).
    ulLCDIndex = MMREADULONG(hGDORageCRT->lpMMR, LCD_INDEX);
    ulLCDIndex &= (~LCD_INDEX__LCD_REG_INDEX_MASK);
    ulLCDIndex |= LCD_INDEX_lcdGenCtrlReg;
    MMWRITEULONG(hGDORageCRT->lpMMR, LCD_INDEX, ulLCDIndex);

    // Read LCD GEN CTRL data from LCD data register first.
    ulLCDGenCtrlData = MMREADULONG(hGDORageCRT->lpMMR, LCD_DATA);

    // Read Gen Ctrl data
    ulCRTCExtCntl_data = MMREADULONG(hGDORageCRT->lpMMR, CRTC_GEN_CNTL);

    switch(ulState)
    {
    case(POWERSTATE_ON):

      //EPR#039657 twdal#4681 Fn+F3 do not turn off CRT on secondary in W2K

      // set CRT_ON bit to 1 which turns on the CRT display.
      ulLCDGenCtrlData |= LCD_GEN_CTRL__CRT_ON;

      // turn the HSYCN_DIS and VSYNC_DIS bits off
      ulCRTCExtCntl_data &= (~CRTC_GEN_CNTL__CRTC_HSYNC_DIS &
                             ~CRTC_GEN_CNTL__CRTC_VSYNC_DIS );

        break;
    case(POWERSTATE_STANDBY):

      //EPR#039657 twdal#4681 Fn+F3 do not turn off CRT on secondary in W2K
      // set CRT_ON bit to 0 which turns off the CRT display.
      ulLCDGenCtrlData &= (~LCD_GEN_CTRL__CRT_ON);

      // turn the HSYCN_DIS bit and make sure the VSYNC_DIS bit is off
      ulCRTCExtCntl_data |= CRTC_GEN_CNTL__CRTC_HSYNC_DIS ;
      ulCRTCExtCntl_data &= ~CRTC_GEN_CNTL__CRTC_VSYNC_DIS;

      break;

    case(POWERSTATE_SUSPEND):

      //EPR#039657 Task twdal#4681 Fn+F3 do not turn off CRT on secondary in W2K
      // set CRT_ON bit to 0 which turns off the CRT display.
      ulLCDGenCtrlData &= (~LCD_GEN_CTRL__CRT_ON);

      // turn the VSYNC_DIS bit on and make sure the HSYNC_DIS bit is off
      ulCRTCExtCntl_data |= CRTC_GEN_CNTL__CRTC_VSYNC_DIS ;
      ulCRTCExtCntl_data &= ~CRTC_GEN_CNTL__CRTC_HSYNC_DIS;

      break;

    case(POWERSTATE_OFF):

      //EPR#039657 twdal#4681 Fn+F3 do not turn off CRT on secondary in W2K
      // set CRT_ON bit to 0 which turns off the CRT display.
      ulLCDGenCtrlData &= (~LCD_GEN_CTRL__CRT_ON);

      // turn the HSYCN_DIS and VSYNC_DIS bits on.
      ulCRTCExtCntl_data |= (CRTC_GEN_CNTL__CRTC_HSYNC_DIS |
                             CRTC_GEN_CNTL__CRTC_VSYNC_DIS );

      break;
    }// end switch

    //EPR#039657 twdal#4681 Fn+F3 do not turn off CRT on secondary in W2K
    //EPR#040854 Disable CRT engine on all POWERSTATE except 
    //POWERSTATE_ON state

    // Write out LCD GEN CTRL data to LCD data register.
    MMWRITEULONG(hGDORageCRT->lpMMR, LCD_DATA, ulLCDGenCtrlData);

    // Write out Gen Ctrl data
    MMWRITEULONG(hGDORageCRT->lpMMR, CRTC_GEN_CNTL, ulCRTCExtCntl_data);

} // end CRTSetDPMS

/******************************Public*Routine******************************\
* VOID CRTGetVericalSyncAdjustment(HGDO hGDO,
*                                  LPHW_ADJUSTMENT lpadjustment,
*                                  LPDEVMODE_INFO lpmi)
*
* CRTGetVericalSyncAdjustment is used to query the minimum, maximum, and
* default values for vertical sync polarity adjustments.
*
\**************************************************************************/
VOID FAR
CRTGetVerticalSyncAdjustment(
    HGDO hGDO,
    LPHW_ADJUSTMENT lpAdjustment,
    LPDEVMODE_INFO lpMI
    )
{
    LPGDO_RAGE_CRT  hGDORageCRT;

    hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;

    DALDEBUG((DALDBG_NORMAL, "ATIRAGE.SYS! GDO-CRT: CRTGetVerticalSyncAdjustment - Entry"));

    // Checks controller number. 0: primary, 1: Secondary
    if ( hGDORageCRT->ulController == PRIMARY_CONTROLLER)
    {
        lpAdjustment[0].lStep = 1;
        lpAdjustment[0].lDefault = (LONG)hGDORageCRT->ucVerticalSync;
        lpAdjustment[0].lMin = 0;
        lpAdjustment[0].lMax = 1;
    }
    else
    {
        lpAdjustment[0].lStep = 0;
        lpAdjustment[0].lDefault = 0;
        lpAdjustment[0].lMin = 0;
        lpAdjustment[0].lMax = 0;
    }

} // end CRTGetVerticalSyncAdjustment

/******************************Public*Routine******************************\
* VOID CRTGetHorizontalSyncAdjustment(HGDO hGDO,
*                                     LPHW_ADJUSTMENT lpadjustment,
*                                     LPDEVMODE_INFO lpmi)
*
* CRTGetHorizontalSyncAdjustment is used to query the minimum, maximum, and
* default values for horizontal sync polarity adjustments.
*
\**************************************************************************/
VOID FAR
CRTGetHorizontalSyncAdjustment(
    HGDO hGDO,
    LPHW_ADJUSTMENT lpAdjustment,
    LPDEVMODE_INFO lpMI
    )
{
    LPGDO_RAGE_CRT  hGDORageCRT;

    hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;

    DALDEBUG((DALDBG_NORMAL, "ATIRAGE.SYS! GDO-CRT: CRTGetHorizontalSyncAdjustment - Entry"));

    // Checks controller number. 0: primary, 1: Secondary
    if ( hGDORageCRT->ulController == PRIMARY_CONTROLLER)
    {
        lpAdjustment[0].lStep = 1;
        lpAdjustment[0].lDefault = (LONG)hGDORageCRT->ucHorizontalSync;
        lpAdjustment[0].lMin = 0;
        lpAdjustment[0].lMax = 1;
    }
    else
    {
        lpAdjustment[0].lStep = 0;
        lpAdjustment[0].lDefault = 0;
        lpAdjustment[0].lMin = 0;
        lpAdjustment[0].lMax = 0;
    }

} // end CRTGetHorizontalSyncAdjustment

/******************************Public*Routine******************************\
* VOID CRTGetCompositeSyncAdjustment(HGDO hGDO,
*                                    LPHW_ADJUSTMENT lpadjustment,
*                                    LPDEVMODE_INFO lpmi)
*
* CRTGetCompositeSyncAdjustment is used to query the minimum, maximum, and
* default values for composite Sync adjustments.
*
\****