📄 ltddc.c
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MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_DATA, ucTemp, 1);
}
else
{
//
// Rage XL: Handle SCL through regular CRT connector.
//
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, LCD_DATA, 3) & // Rage XL
~(0x40))| (ucData << 6);
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_DATA, ucTemp, 3);
}
}
}
} // DDC2_I2CWriteClockLine()
VOID
DDC2_I2CWriteDataLine(
HGDO hGDO,
HDDL hDDL,
UCHAR ucData
)
//
// DESCRIPTION:
// Sets DDC I2C data line (SDA) low / high.
//
// PARAMETERS:
// hDDL Points to per-adapter device extension.
// ucData 0 = drive SDA low, 1 = drive SDA high.
//
{
LPGDO_RAGE_CRT hGDORageCRT;
UCHAR ucTemp;
DALASSERT(NULL != hDDL, "hDDL is NULL!");
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
ucData &= 0x01; // Mask
if (FAMILY_GTC == (hGDORageCRT->ulChipFamily))
{
//rage pro specific code
ucTemp = (UCHAR)(MMREADUCHAR(hGDORageCRT->lpMMR, GP_IO, 3) | (0x01 << 4));
MMWRITEUCHAR(hGDORageCRT->lpMMR, GP_IO, ucTemp, 3);
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, GP_IO, 1) & ~(0x01 << 4)) | (ucData<< 4);
MMWRITEUCHAR(hGDORageCRT->lpMMR, GP_IO, ucTemp, 1);
}
else
{
ucData ^= 0x01; // Invert
//
// Set the SDA enable line.
//
if( hGDORageCRT->ulChipFamily == FAMILY_LT_PRO||
hGDORageCRT->ulChipFamily == FAMILY_RAGE_MOBILITY)
{
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, LCD_DATA, 3) &
~(0x40)) | (ucData << 6);
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_DATA, ucTemp, 3);
}
else
{
// EPR 35356.
if (hGDORageCRT->bREADEDIDFROMDVI == TRUE)
{
//
// Rage XL: Handle SDA through DVI connector. (Same as DFP)
//
// Set LCD_DATA register to index 28 (LCD_INDEX_TEST_IO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_TestIO, 0);
//
// Set the SDA enable line (Rage XL).
//
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, LCD_DATA, 1) &
~(0x02)) | (ucData << 1);
if (ucData)
{
ucTemp &= ~(0x08);
}
MMWRITEUCHAR(hGDORageCRT->lpMMR,
LCD_DATA, ucTemp, 1);
}
else
{
//
// Rage XL: Handle SDA through regular CRT connector.
//
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, LCD_DATA, 3) & // Rage XL
~(0x20)) | (ucData << 5);
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_DATA, ucTemp, 3);
}
}
}
} // DDC2_I2CWriteDataLine()
BOOLEAN
DDC2_I2CReadClockLine(
HGDO hGDO,
HDDL hDDL
)
//
// DESCRIPTION:
// Reads DDC I2C clock line (SCL).
//
// PARAMETERS:
// hDDL Points to per-adapter device extension.
//
// RETURN VALUE:
// TRUE SCL high.
// FALSE SCL low.
//
{
LPGDO_RAGE_CRT hGDORageCRT;
DALASSERT(NULL != hDDL, "hDDL is NULL!");
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
//sunnyvale [vichan] port by [espiritu]
if (FAMILY_GTC == (hGDORageCRT->ulChipFamily))
{
UCHAR ucTemp;
ucTemp = (UCHAR)(MMREADUCHAR(hGDORageCRT->lpMMR, GP_IO, 3) & ~(0x01 << 5));
MMWRITEUCHAR(hGDORageCRT->lpMMR, GP_IO, ucTemp, 3);
return((BOOLEAN) ((MMREADUCHAR(hGDORageCRT->lpMMR, GP_IO, 1) >> 5) & 0x01));
}
else
{
//
// Read from the SCL line and return.
//
if( hGDORageCRT->ulChipFamily == FAMILY_LT_PRO||
hGDORageCRT->ulChipFamily == FAMILY_RAGE_MOBILITY)
{
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
return (BOOLEAN)((MMREADUCHAR(hGDORageCRT->lpMMR,
LCD_DATA, 1) >> 5) & 0x01);
}
else
{
// EPR 35356.
if (hGDORageCRT->bREADEDIDFROMDVI == TRUE)
{
//
// Rage XL: Handle SCL through DVI connector. (Same as DFP)
//
// Set LCD_DATA register to index 28 (LCD_INDEX_TEST_IO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_TestIO, 0);
//
// Read from the SCL line and return (Rage XL).
//
return (BOOLEAN)((MMREADUCHAR(hGDORageCRT->lpMMR,
LCD_DATA, 1) >> 2) & 0x01);
}
else
{
//
// Rage XL: Handle SCL through regular CRT connector.
//
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
return (BOOLEAN)((MMREADUCHAR(hGDORageCRT->lpMMR, // Rage XL
LCD_DATA, 1) >> 6) & 0x01);
}
}
}
} // DDC2_I2CReadClockLine()
BOOLEAN
DDC2_I2CReadDataLine(
HGDO hGDO,
HDDL hDDL
)
//
// DESCRIPTION:
// Reads DDC I2C data line (SDA).
//
// PARAMETERS:
// hDDL Points to per-adapter device extension.
//
// RETURN VALUE:
// TRUE SDA high.
// FALSE SDA low.
//
{
LPGDO_RAGE_CRT hGDORageCRT;
DALASSERT(NULL != hDDL, "hDDL is NULL!");
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
if (FAMILY_GTC == (hGDORageCRT->ulChipFamily))
{
UCHAR ucTemp;
ucTemp = (UCHAR)(MMREADUCHAR(hGDORageCRT->lpMMR, GP_IO, 3) & ~(0x01 << 4));
MMWRITEUCHAR(hGDORageCRT->lpMMR, GP_IO, ucTemp, 3);
return((BOOLEAN) ((MMREADUCHAR(hGDORageCRT->lpMMR, GP_IO, 1) >> 4) & 0x01));
}
else
{
//
// Read from the SDA line and return.
//
if( hGDORageCRT->ulChipFamily == FAMILY_LT_PRO||
hGDORageCRT->ulChipFamily == FAMILY_RAGE_MOBILITY)
{
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
return (BOOLEAN)((MMREADUCHAR(hGDORageCRT->lpMMR,
LCD_DATA, 1) >> 6) & 0x01);
}
else
{
// EPR 35356.
if (hGDORageCRT->bREADEDIDFROMDVI == TRUE)
{
//
// Rage XL: Handle SDA through DVI connector. (Same as DFP)
//
// Set LCD_DATA register to index 28 (LCD_INDEX_TEST_IO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_TestIO, 0);
//
// Read from the SDA line and return (Rage XL).
//
return (BOOLEAN)((MMREADUCHAR(hGDORageCRT->lpMMR,
LCD_DATA, 1) >> 3) & 0x01);
}
else
{
//
// Rage XL: Handle SDA through regular CRT connector.
//
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
return (BOOLEAN)((MMREADUCHAR(hGDORageCRT->lpMMR, // Rgae XL
LCD_DATA, 1) >> 5) & 0x01);
}
}
}
} // DDC2_I2CReadDataLine()
VOID
WaitForVerticalBlank(
HGDO hGDO,
HDDL hDDL
)
//
// DESCRIPTION:
// Waits for beginning of new vertical blank.
//
// PARAMETERS:
// hDDL Points to per-adapter device extension.
//
{
LPGDO_RAGE_CRT hGDORageCRT;
DALASSERT(NULL != hDDL, "hDDL is NULL!");
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
if ( hGDORageCRT->ulController == PRIMARY_CONTROLLER)
{
while (IS_CRTC_VERTICAL_BLANK(hGDORageCRT->lpMMR) == TRUE);
while (IS_CRTC_VERTICAL_BLANK(hGDORageCRT->lpMMR) == FALSE);
}
else
{
while (IS_CRTC2_VERTICAL_BLANK(hGDORageCRT->lpMMR) == TRUE);
while (IS_CRTC2_VERTICAL_BLANK(hGDORageCRT->lpMMR) == FALSE);
}
}
// EPR 40230
/******************************Public*Routine******************************\
* VOID vEnsureCRTON(HGDO hGDO)
*
* This routine checks LCD_GEN_CNTL register to ensure CRTC_ON bit is ON.
*
\**************************************************************************/
VOID
vEnsureCRTON(HGDO hGDO)
{
ULONG ulLCDGenCtrlData;
ULONG ulLCDIndex;
LPGDO_RAGE_CRT hGDORageCRT;
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
// EPR 40230
// if CRTC_ON bit is cleared.
// 1. Set CRTC_ON bit to 1.
// 2. Black CRT screen.
//
if( hGDORageCRT->ulRetryCounter > DEFAULT_RETRY_COUNTER )
{
// Set LCD_DATA register to index 1( LCD_GEN_CTRL).
ulLCDIndex = MMREADULONG(hGDORageCRT->lpMMR, LCD_INDEX);
ulLCDIndex &= (~LCD_INDEX__LCD_REG_INDEX_MASK);
ulLCDIndex |= LCD_INDEX_lcdGenCtrlReg;
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_INDEX, ulLCDIndex);
// Read LCD GEN CTRL data from LCD data register first.
ulLCDGenCtrlData = MMREADULONG(hGDORageCRT->lpMMR, LCD_DATA);
if(!(ulLCDGenCtrlData & LCD_GEN_CTRL__CRT_ON))
{
hGDORageCRT->ulFlag |= CLEAR_CRT_ON_BIT;
// set CRT_ON bit to 1.
ulLCDGenCtrlData |= LCD_GEN_CTRL__CRT_ON;
// Write out LCD GEN CTRL data to LCD data register.
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_DATA, ulLCDGenCtrlData);
// DDC routines need to turn on CRT for short period of time.
// To prevent any image display on CRT, black CRT screen is
// necessary.
vBlackCRTScreen( hGDO );
}
}
} // End vEnsureCRTON
// EPR 40230
/******************************Public*Routine******************************\
* VOID vBlackCRTScreen(HGDO hGDO)
*
* This routine black CRT screen
*
\**************************************************************************/
VOID
vBlackCRTScreen(HGDO hGDO)
{
ULONG ulLCDMiscCntlData;
ULONG ulLCDIndex;
LPGDO_RAGE_CRT hGDORageCRT;
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
// Set LCD_DATA register to index 14( LCD_MISC_CNTL).
ulLCDIndex = MMREADULONG(hGDORageCRT->lpMMR, LCD_INDEX);
ulLCDIndex &= (~LCD_INDEX__LCD_REG_INDEX_MASK);
ulLCDIndex |= LCD_INDEX_LcdMiscCntl;
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_INDEX, ulLCDIndex);
// Read LCD_MISC_CNTL data from LCD data register first.
hGDORageCRT->ulLCDMiscCntlOrg =
ulLCDMiscCntlData = MMREADULONG(hGDORageCRT->lpMMR, LCD_DATA);
//
// Set MONITOR_DET_EN to 1.
// Set FORCE_DAC_DATA_SEL to 3.
// Set FORCE_DAC_DATA to 0.
//
ulLCDMiscCntlData |= (LCD_MISC_CNTL__FORCE_DAC_DATA_SEL_MASK |
LCD_MISC_CNTL__MONITOR_DET_EN);
ulLCDMiscCntlData &= (~LCD_MISC_CNTL__FORCE_DAC_DATA_MASK);
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_DATA, ulLCDMiscCntlData);
} // End vBlackCRTScreen
// EPR 40230
/******************************Public*Routine******************************\
* VOID vRestoreCRTON(HGDO hGDO)
*
* This routine clear CRTC_ON bit and unblack CRT screen if necessary.
*
\**************************************************************************/
VOID
vRestoreCRTON(HGDO hGDO)
{
ULONG ulLCDIndex;
LPGDO_RAGE_CRT hGDORageCRT;
ULONG ulLCDGenCtrlData;
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
if(hGDORageCRT->ulFlag & CLEAR_CRT_ON_BIT)
{
hGDORageCRT->ulFlag &= ~CLEAR_CRT_ON_BIT;
// Set LCD_DATA register to index 1( LCD_GEN_CTRL).
ulLCDIndex = MMREADULONG(hGDORageCRT->lpMMR, LCD_INDEX);
ulLCDIndex &= (~LCD_INDEX__LCD_REG_INDEX_MASK);
ulLCDIndex |= LCD_INDEX_lcdGenCtrlReg;
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_INDEX, ulLCDIndex);
ulLCDGenCtrlData = MMREADULONG(hGDORageCRT->lpMMR, LCD_DATA);
// Clear CRT_ON bit.
ulLCDGenCtrlData &= ~LCD_GEN_CTRL__CRT_ON;
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_DATA, ulLCDGenCtrlData);
// Set LCD_DATA register to index 14( LCD_MISC_CNTL).
ulLCDIndex &= (~LCD_INDEX__LCD_REG_INDEX_MASK);
ulLCDIndex |= LCD_INDEX_LcdMiscCntl;
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_INDEX, ulLCDIndex);
// Restore orginal value of LCD_MISC_CNTL register which unblack CRT.
MMWRITEULONG(hGDORageCRT->lpMMR, LCD_DATA, hGDORageCRT->ulLCDMiscCntlOrg);
}
} // End vRestoreCRTON
// EPR 40230
VOID vInitializeLT_GIO(HGDO hGDO)
{
LPGDO_RAGE_CRT hGDORageCRT;
UCHAR ucTemp;
hGDORageCRT = (LPGDO_RAGE_CRT)hGDO;
// Set LCD_DATA register to index 7 (LCD_INDEX_LT_GIO).
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_INDEX, LCD_INDEX_LtGio, 0);
// Set GPIO_15 & 16 direction to output.
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, LCD_DATA, 3) |
LT_GIO_GPIO15_16);
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_DATA, ucTemp, 3);
// Clear GPIO 15 & 16;
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, LCD_DATA, 1) &
~(LT_GIO_GPIO15_16));
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_DATA, ucTemp, 1);
// Reset GPIO_15 & 16 direction to input.
ucTemp = (MMREADUCHAR(hGDORageCRT->lpMMR, LCD_DATA, 3) &
~(LT_GIO_GPIO15_16));
MMWRITEUCHAR(hGDORageCRT->lpMMR, LCD_DATA, ucTemp, 3);
}
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