crtcrpro.c

此代码为WCE5.0下显示器的源代码

    }

    // Start at the first entry.
    lpLookupCapData = lpFirstCapMode;

    // Find this mode in the cap table.
    while ((lpMI->ulPelsWidth    != lpLookupCapData->ulHorizontalResolution) ||
           (lpMI->ulPelsHeight   != lpLookupCapData->ulVerticalResolution)   ||
           (lpMI->ulBitsPerPixel != lpLookupCapData->ulPixelDepth)           ||
           (((ULONG)(lpLookupModeData->BiosCrtcTiming.usPixelClock) * 10000) > lpLookupCapData->ulMaxPixelClock))
    {
        if (0 == lpLookupCapData->ulHorizontalResolution)
        {
            DALDEBUG((DALDBG_NORMAL, "ATIRAGE RageProIsNonStandardModeSupported: mode not in cap table"));
            return FALSE;           // TODO: Later use GTFs to determine if mode can be supported.
        }

        lpLookupCapData++;
    }

    // Use VESA's Generalized Timing Formulas to calculate whether the mode is possible.

    DALDEBUG((DALDBG_NORMAL, "ATIRAGE RageProIsNonStandardModeSupported: mode is supported"));
    DALDEBUG((DALDBG_ENTRY_EXIT, "ATIRAGE RageProIsNonStandardModeSupported: *** exit ***"));

    return TRUE;

}   // RageProIsNonStandardModeSupported()


//
// DESCRIPTION:
//  RageProPreModeChange performs any pre-mode configuration required by
//  the controller before a mode change occurs.
//
// PARAMETERS:
//  hGCO            Handle of the controller object structure, which
//                  uniquely identifies the graphics controller object.
//  lpMI            Points to the mode information structure to be
//                  filled with the mode information of the specific mode
//                  index.
//  ulController    Specifies a bit vector specifying a single controller
//                  whose standard modes are being enumerated.
//
// RETURN VALUE:
//  None
//
VOID FAR RageProPreModeChange(
    HGCO hGCO,
    LPDEVMODE_INFO lpMI,
    ULONG ulControllers
    )
{
    LPHW_RAGEPROCRTC_EXTENSION lpHwCrtc = (LPHW_RAGEPROCRTC_EXTENSION)hGCO;

    DALDEBUG((DALDBG_ENTRY_EXIT, "ATIRAGE RageProPreModeChange: *** entry point ***"));
    DALDEBUG((DALDBG_NORMAL, "ATIRAGE RageProPreModeChange: no code"));
    DALDEBUG((DALDBG_ENTRY_EXIT, "ATIRAGE RageProPreModeChange: *** exit ***"));
}   // RageProPreModeChange()


//
// DESCRIPTION:
//  RageProPostModeChange performs any post-mode configuration or cleanup
//  required by the controller after a mode change occurs.
//
// PARAMETERS:
//  hGCO            Handle of the controller object structure, which
//                  uniquely identifies the graphics controller object.
//  pMI             Points to the mode information structure to be
//                  filled with the mode information of the specific mode
//                  index.
//  ulController    Specifies a bit vector specifying a single controller
//                  whose standard modes are being enumerated.
//
// RETURN VALUE:
//  None
//
VOID FAR RageProPostModeChange(
    HGCO hGCO,
    LPDEVMODE_INFO lpMI,
    ULONG ulControllers
    )
{
    LPHW_RAGEPROCRTC_EXTENSION lpHwCrtc = (LPHW_RAGEPROCRTC_EXTENSION)hGCO;

    DALDEBUG((DALDBG_ENTRY_EXIT, "ATIRAGE RageProPostModeChange: *** entry point ***"));
    DALDEBUG((DALDBG_NORMAL, "ATIRAGE RageProPostModeChange: no code"));
    DALDEBUG((DALDBG_ENTRY_EXIT, "ATIRAGE RageProPostModeChange: *** exit ***"));
}   // RageProPostModeChange()


VOID FAR RageProAcceleratorToVgaMode(HGCO hGCO)
{
    ULONG ulTemp, ulTemp2;

    LPHW_RAGEPROCRTC_EXTENSION lpHwCrtc = (LPHW_RAGEPROCRTC_EXTENSION)hGCO;

    if(lpHwCrtc->HwAsicId.ulChipFamily == FAMILY_LT_PRO)
    {
        ulTemp  = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, LCD_INDEX);
        // Disable the display from secondary CRTC
        ulTemp |= LCD_INDEX_Crtc2DisplayDis;
        // Attach LCD to primary controller
        ulTemp &= ~LCD_INDEX_LcdSrcSel;

        MMWRITEULONG(lpHwCrtc->HwAsicId.lpMMR, LCD_INDEX, ulTemp);

        ulTemp  = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, DAC_CNTL);
        // Attach monitor to primary controller
        ulTemp &= ~DAC_CNTL_Dac1ClkSel;
        // Select access to primary palette
        ulTemp &= ~DAC_CNTL_PalAccessCntl;

        MMWRITEULONG(lpHwCrtc->HwAsicId.lpMMR, DAC_CNTL, ulTemp);

        ulTemp  = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, CRTC_GEN_CNTL);
        // Enable Crtc1
        ulTemp |= CRTC_GEN_CNTL_CrtcEnable;
        // Disable Crtc2
        ulTemp &= ~CRTC_GEN_CNTL_Crtc2Enable;

        MMWRITEULONG(lpHwCrtc->HwAsicId.lpMMR, CRTC_GEN_CNTL, ulTemp);

        // Restore CRTC_RW_SELECT bit to allow register read/writes to go to primary
        ulTemp  = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, LCD_INDEX);
        ulTemp &= lpHwCrtc->ulLCDIndexRegisterMask;
        // Now also setup the index to do read/write operation on LCD_GEN_CTRL registers
        MMWRITEULONG(lpHwCrtc->HwAsicId.lpMMR, LCD_INDEX, (ulTemp | LCD_INDEX_lcdGenCtrlReg));

        // Save LCD_GEN_CTRL register value
        ulTemp = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, LCD_DATA);
        // All CRTC registers reads/writes go to primary CRTC
        ulTemp &= ~LCD_GEN_CTL_CrtcRWSelect;

        // Read the scratch register, where the bios saves device configuration status
        // and according to the previos state of bios restore the appropriate Registers
        ulTemp2 = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, SCRATCH_REG3);

        if(ulTemp2 & BIOS_LCD_ON)
        {
            // Enable use of the shadow registers, BIOS expects this to be on for LCD attached
            ulTemp |= LCD_GEN_CTL_LcdShadowEn;
        }

        //Load the value to LCD_GEN_CTRL register
        MMWRITEULONG(lpHwCrtc->HwAsicId.lpMMR, LCD_DATA, ulTemp);

        if(ulTemp2 & BIOS_CRT_ON)
        {
            // restore CRT specific stuff if any
        }

        if(ulTemp2 & BIOS_TVO_ON)
        {
            // restore TV specific stuff if any
        }
    }

}


//
// DESCRIPTION:
//  RageProSetGammaCorrection is used to program the gamma correction for
//  a graphics controller.
//
// PARAMETERS:
//  hGCO            Handle of the controller object structure, which
//                  uniquely identifies the graphics controller object.
//  ulController    Specifies a bit vector specifying a single controller
//                  whose standard modes are being enumerated.
//  aGamma          Points to an array of DEVCLUT structures containing
//                  the 24bpp colors to retrieve the gamma correction
//                  default values.
//
// RETURN VALUE:
//  None
//
VOID FAR RageProSetGammaCorrection( HGCO hGCO, ULONG ulController, LPDEVCLUT lpaGamma)
{

    //DEVCLUT aPalette[256];
    ULONG   ulcounter;
    ULONG   ulindex, ulindex2;
    ULONG   ulDacIndex;
    ULONG   ulTemp;
    ULONG   ulCurrentBitsPerPixel;
    UCHAR   ucTemp, ucAddress, ucData, ucPllGenCntl;
    LPHW_RAGEPROCRTC_EXTENSION lpHwCrtc = (LPHW_RAGEPROCRTC_EXTENSION)hGCO;

    DALDEBUG((DALDBG_ENTRY_EXIT, "RAGEMP RageProSetGammaCorrection: *** entry point ***"));

    DALASSERT(NULL != lpaGamma, "Array of palette colours is NULL");

    // Select which controller's palette to set
    //if(lpHwCrtc->HwAsicId.ulChipFamily == FAMILY_LT_PRO)
    if((lpHwCrtc->ulGCOSupportedRegSet & RAGE_LTPRO_REGISTER_SET) &&
       (lpHwCrtc->ulGCOSupportedRegSet & RAGE_PRO_CRTC2_REGISTER_SET))
    {
        ulTemp  = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, CRTC_GEN_CNTL); // Read the Crtc_Gen_Cntl Register

        if( ulController == PRIMARY_CONTROLLER )
        {
            if(!(ulTemp & CRTC_GEN_CNTL_CrtcEnable))
            {
                return; //crtc is disabled waiting for blank is not safe
            }

            ulTemp  = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, DAC_CNTL);
            ulTemp &= ~DAC_CNTL_PalAccessCntl;
            MMWRITEULONG(lpHwCrtc->HwAsicId.lpMMR, DAC_CNTL, ulTemp);
            // Fix to remove sparkling effect that occurs when repeatedly writing to the palette.
            // [cd]: while (FALSE == IS_VERTICAL_BLANK(lpHwCrtc->HwAsicId.lpMMR));
        }
        else if (ulController == SECONDARY_CONTROLLER)
        {
            if(!(ulTemp & CRTC_GEN_CNTL_Crtc2Enable))
            {
                return;
            }

            ulTemp  = MMREADULONG(lpHwCrtc->HwAsicId.lpMMR, DAC_CNTL);
            ulTemp |= DAC_CNTL_PalAccessCntl;
            MMWRITEULONG(lpHwCrtc->HwAsicId.lpMMR, DAC_CNTL, ulTemp);

            // There is some hardware bug in Rage mobility when accessing secondary palette.
            // As per Alex [22 Mar 99] temporary fix is to slow down SCLK
            // read or write the pallette and then restore the clock.
            // [sah] 23 Mar 99.
            if(lpHwCrtc->ulGCOSupportedRegSet & EXT_MOBILITY_REGISTER_SET)
            {
                ucAddress = PLL_GEN_CNTL;
                ucPllGenCntl = GcoPLLReadByte(hGCO, ucAddress);

                if((ucPllGenCntl & PLL_GEN_CNTL_MclkScrSel) == MCLK_EQU_SCLK)
                {
                    ucAddress = SPLL_CNTL2;
                    ucTemp = GcoPLLReadByte(hGCO, ucAddress);

                    ucAddress = SPLL_CNTL2;
                    ucData = 0x30;  // Set SCLK = PLLSCLK/8 to lower the MCLK
                    GcoPLLWriteByte(hGCO, ucAddress, ucData, 0x8F);
                }
                else
                {
                  ucAddress = PLL_GEN_CNTL;
                  ucData = MCLK_EQU_PLLMCLK_DIV8;
                  GcoPLLWriteByte(hGCO, ucAddress, ucData, (UCHAR)(~PLL_GEN_CNTL_MclkScrSel));

                }
            }

            // Fix to remove sparkling effect that occurs when repeatedly writing to the palette.
            // [cd]: while (FALSE == IS_VERTICAL_BLANK2(lpHwCrtc->HwAsicId.lpMMR));
        }
    }

    ulCurrentBitsPerPixel = GetActualPixWidth(hGCO, lpHwCrtc->CurrentModeInfo[ulController].ulBitsPerPixel);

    switch (ulCurrentBitsPerPixel)
    {
        case 8:
        {

            DALDEBUG((DALDBG_NORMAL, "ATIRAGE RageProSetGammaCorrection: Setting gamma for 8 bpp"));
            /*
            MMWRITEUCHAR(lpHwCrtc->HwAsicId.lpMMR, DAC_REGS, 0xFF, 2);  // Set DAC_MASK
            MMWRITEUCHAR(lpHwCrtc->HwAsicId.lpMMR, DAC_REGS, 0x00, 3);  // Set DAC_R_INDEX

            for