📄 rprod.h
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#define DAC_CNTL_DacCmpOutput 0x00000080
#define DAC_CNTL_Dac1ClkSel 0x00000010
#define DAC_CNTL_Dac8BitEn 0x00000100
#define DAC_CNTL_PalAccessCntl 0x00000020
#define DAC_CNTL_DacVgaAdrEn 0x00002000
#define GEN_TEST_CNTL_GuiReset 0x00000100
#define GEN_TEST_CNTL_SoftReset 0x00000200
#define CONFIG_CNTL_CfgVgaDis 0x00080000
#define CONFIG_STAT0_CfgMemType 0x00000007
#define CONFIG_STAT0_CfgVgaEn 0x00000010
#define CONFIG_STAT0_PanelID_Mask 0x001F0000
#define GUI_STAT_GuiActive 0x00000001
#define DAC_REGS_DacData 0x0000FF00
#define DAC_REGS_DacMask 0x00FF0000
#define OVERLAY_SCALE_CNTL_GammaSel 0x00000060
#define OVERLAY_SCALE_CNTL_OverlaySel 0x00000080 // Rage Mobility
#define SCALER_COLOUR_CNTL_Brightness 0x0000007F
// GDO-Specific Masks:
// REGISTER: Scratch Pad and Test
#define SCRATCH_REG2__LCD_CONNECTED_MASK 0x00000001
#define SCRATCH_REG2__CRT_MONO 0x00000002
#define SCRATCH_REG2__CRT_COLOR 0x00000004
#define SCRATCH_REG2__TV_COMPOSITE 0x00000010
#define SCRATCH_REG2__TV_SVIDEO 0x00000020
#define SCRATCH_REG2__LCD_LID_CLOSED_MASK 0x00001000
#define SCRATCH_REG2__REQ_LCD 0x00010000
#define SCRATCH_REG2__REQ_CRT 0x00020000
#define SCRATCH_REG2__REQ_TV 0x00040000
#define SCRATCH_REG2__CRTC_LCD 0x00100000
#define SCRATCH_REG2__CRTC_CRT 0x00200000
#define SCRATCH_REG2__CRTC_TV 0x00400000
#define SCRATCH_REG2__H_EXPNAD_TEXT 0x01000000
#define SCRATCH_REG2__H_EXPNAD_GRAPH 0x02000000
#define SCRATCH_REG2__V_EXPNAD_TEXT 0x04000000
#define SCRATCH_REG2__V_EXPNAD_GRAPH 0x08000000
#define SCRATCH_REG3__LCD_ACTIVE 0x00000001
#define SCRATCH_REG3__CRT_ACTIVE 0x00000002
#define SCRATCH_REG3__TV_ACTIVE 0x00000004
#define SCRATCH_REG3__CRTC_LCD_ACTIVE 0x00000010
#define SCRATCH_REG3__CRTC_CRT_ACTIVE 0x00000020
#define SCRATCH_REG3__CRTC_TV_ACTIVE 0x00000040
#define SCRATCH_REG3__DISPLAY_SWITCH_DISABLE 0x08000000
#define SCRATCH_REG3__LARGE_DESKTOP_ENABLED 0x10000000
#define SCRATCH_REG3__DUAL_CRTC_MODE 0x20000000
// REGISTER: CRT
#define CLOCK_CNTL__CLOCK_SEL_MASK 0x00000003
#define CLOCK_CNTL__PLL_WR_EN 0x00000200
#define CLOCK_CNTL__PLL_ADDR_MASK 0x00007C00
#define CLOCK_CNTL__PLL_ADDR5 0x00008000
#define CLOCK_CNTL__PLL_DATA_MASK 0x00ff0000
#define CRTC_GEN_CNTL__CRTC_HSYNC_DIS 0x00000004
#define CRTC_GEN_CNTL__CRTC_VSYNC_DIS 0x00000008
#define CRTC_GEN_CNTL__CRTC_CSYNC_EN 0x00000010
#define CRTC_GEN_CNTL__CRTC_DISPLAY_DIS 0x00000040
// REGISTER: CRTC_H_TOTAL_DISP
#define CRTC_H_TOTAL_DISP__CRTC_H_TOTAL_MASK 0x000001ff
#define CRTC_H_TOTAL_DISP__CRTC_H_DISP_MASK 0x01ff0000
// REGISTER: CRTC_V_TOTAL_DISP
#define CRTC_V_TOTAL_DISP__CRTC_V_TOTAL_MASK 0x000007ff
#define CRTC_V_TOTAL_DISP__CRTC_V_DISP_MASK 0x07ff0000
// REGISTER: CRTC_H_SYNC_STRT_WID
#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_ALL_MASK 0x000100ff
#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_MASK 0x000000ff
#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_DLY_MASK 0x00000700
#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_STRT_HI_MASK 0x00001000
#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_WID_MASK 0x001f0000
#define CRTC_H_SYNC_STRT_WID__CRTC_H_SYNC_POL 0x00200000
// REGISTER: CRTC_V_SYNC_STRT_WID
#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_STRT_MASK 0x000007ff
#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_WID_MASK 0x001f0000
#define CRTC_V_SYNC_STRT_WID__CRTC_V_SYNC_POL 0x00200000
// REGISTER: OVR_WID_LEFT_RIGHT
#define OVR_WID_LEFT_RIGHT__OVR_WID_LEFT_MASK 0x0000003f
#define OVR_WID_LEFT_RIGHT__OVR_WID_RIGHT_MASK 0x003f0000
// REGISTER: OVR_WID_TOP_BOTTOM
#define OVR_WID_TOP_BOTTOM__OVR_WID_TOP_MASK 0x000001ff
#define OVR_WID_TOP_BOTTOM__OVR_WID_BOTTOM_MASK 0x01ff0000
// REGISTER: DAC_CNTL
#define DAC_CNTL__DAC_RANGE_CNTL_MASK 0x00000003
#define DAC_CNTL__DAC_BLANKING 0x00000004
#define DAC_CNTL__DAC_CMP_DIS 0x00000008
#define DAC_CNTL__DAC1_CLK_SEL 0x00000010
#define DAC_CNTL__DAC_CMP_OUTPUT 0x00000080
#define DAC_CNTL__DAC_8BIT_EN 0x00000100
#define DAC_CNTL__CRTSense 0x00000800
#define DAC_CNTL__CRTDetectionOn 0x00001000
#define DAC_CNTL__DAC_VGA_ADR_EN 0x00002000
#define DAC_CNTL__DAC_PDWN 0x00008000
// REGISTER: TIMER_CONFIG
#define TIMER_CONFIG__PM_DSP_RW_SEL 0x80000000
// REGISTER: CRTC_VLINE_CRNT_VLINE
#define CRTC_VLINE_CRNT_VLINE__CRTC_VLINE_MASK 0x000007ff
#define CRTC_VLINE_CRNT_VLINE__CRTC_CRNT_VLINE_MASK 0x07ff0000
// REGISTER: HTOTAL_CNTL
#define HTOTAL_CNTL__HTOT_PPLL_SLIP_MASK 0x07
#define HTOTAL_CNTL__HTOT_CNTL_EDGE 0x78
#define HTOTAL_CNTL__HTOT_CNTL_VGA_EN 0x80
// REGISTER: LCD_INDEX
#define LCD_INDEX__LCD_REG_INDEX_MASK 0x0000003f
#define LCD_INDEX__LCD_DISPLAY_DIS 0x00000100
#define LCD_INDEX__LCD_SRC_SEL 0x00000200
#define LCD_INDEX__CRTC2_DISPLAY_DIS 0x00000400
#define LCD_INDEX__GUI_ACTIVE 0x00000800
#define LCD_INDEX__MONDET_SENSE 0x01000000
#define LCD_INDEX__MONDET_INT_POL 0x02000000
#define LCD_INDEX__MONDET_INT_EN 0x04000000
#define LCD_INDEX__MONDET_INT 0x08000000
#define LCD_INDEX__MONDET_INT_ACK 0x08000000
#define LCD_INDEX__MONDET_EN 0x10000000
// REGISTER: CONFIG_PANEL_MASK
#define CONFIG_PANEL__BIAS_LEVEL_MASK 0x0C000000
#define CONFIG_PANEL__BLINK_RATE_MASK 0x00002000
#define CONFIG_PANEL__PANEL_TYPE_MASK 0x000000f0
#define CONFIG_PANEL__PANEL_TYPE_DSTN 0x00000010
// REGISTER: DSTN_CONTROL
#define DSTN_CONTROL__FP_POS_MASK 0x000007FF
#define DSTN_CONTROL__LOWER_PANEL_VPOS_MASK 0x003FF000
#define DSTN_CONTROL__AUTO_LOWER_PANEL_VPOS 0x00400000
// REGISTER: LCD_GEN_CTRL
#define LCD_GEN_CTRL__CRT_ON 0x00000001
#define LCD_GEN_CTRL__LCD_ON 0x00000002
// REGISTER: LCD_MISC_CNTL
#define LCD_MISC_CNTL__MONITOR_DET_EN 0x00200000
#define LCD_MISC_CNTL__FORCE_DAC_DATA_SEL_MASK 0x00C00000
#define LCD_MISC_CNTL__FORCE_DAC_DATA_MASK 0xff000000
// REGISTER: POWER_MANAGEMENT
#define POWER_MANAGEMENT__BLON 0x02000000
#define POWER_MANAGEMENT__DIGON 0x04000000
// REGISTER: LCD_MISC_CTRL
#define LCD_MISC_CTRL__PL_EN 0x00040000
// REGISTER PL_TRANSMITTER_CNTL
#define PL_TRANSMITTER_CNTL__PPLLEN 0x00000001
#define PL_TRANSMITTER_CNTL__PPLLRST 0x00000002
// REGISTER: I2C_CNTL_0
#define CNTL_0__I2C_CNTL_SCL 0x00004000
#define CNTL_0__I2C_CNTL_SDA 0x00008000
// REGISTER: I2C_CNTL_1
#define CNTL_1__I2C_SEL0 0x00400000
#define CNTL_1__I2C_SEL1 0x00800000
//
// *** CONSTANTS ***
//
#define CV_RAGEPRO_1 1
// Additional GCO stuff.
#define PRIMARY_CONTROLLER 0x00
#define SECONDARY_CONTROLLER 0x01
#define HW_DISPLAY_TV_NTSC 0x0010
#define HW_DISPLAY_TV_PAL 0x0020
#define EXT_VPLL_CNTL_ExtVpllEn 0x04
#define EXT_VPLL_CNTL_ExtVpllVgaEn 0x08
#define EXT_VPLL_CNTL_ExtV2pllInsync 0x80
#define EXT_VPLL_CNTL_ExtVpllInsync 0x10
#define EXT_VPLL_CNTL_ExtV2pllEn 0x80
#define EXT_VxPLL_MSB_ExtVpllFbDiv 0x70
#define EXT_V2PLL_MSB_ExtVpllFbDiv 0x70
#define EXT_VPLL_MSB_ExtVpllFbDiv 0x70
#define EXT_VxPLL_MSB_ExtVpllRefDiv 0x03
#define EXT_V2PLL_MSB_ExtVpllRefDiv 0x03
#define EXT_VPLL_MSB_ExtVpllRefDiv 0x03
#define EXT_VxPLL_MSB_ExtVpllUpdate 0x08
#define EXT_V2PLL_MSB_ExtVpllUpdate 0x08
#define EXT_VPLL_MSB_ExtVpllUpdate 0x08
#define HTOTAL2_CNTL_ExtV2pllInsync 0x80
#define PM_DYN_CLK_CNTL_SsEn 0x80
//
// TODO: We are using hardcoded RAGE PRO values for testing only.
// They can be read from ROM header there 16-17 = progclk_entries, 2-3 = min_freq / 12, 4-5 = max_freq,
// 8-9 = ref_freq, 10-11 = ref_divider.
//
#define CRYSTAL_FREQ_1432 1432 //MHz
#define CRYSTAL_FREQ_2863 2863 //MHz
#define CRYSTAL_FREQ_2950 2950 //MHz
#define UPTO_2_DEC_POINT 2
#define UPTO_3_DEC_POINT 3
#define UPTO_4_DEC_POINT 4
#define UPTO_5_DEC_POINT 5
#define MCLK_SRC 16500
#define DRAM_XCLK 8300
#define MFB_TIMES_4_2b 0x08
#define CX_PROG_CLK 3 // VCLK3 for coprocessor mode
#define PLL_DIV1 0x0000
#define PLL_DIV2 0x0001
#define PLL_DIV4 0x0002
#define PLL_DIV8 0x0003
#define PLL_EXTDIV 0x0004
#define PLL_DIV3 0x0004
#define PLL_DIV5 0x0005
#define PLL_DIV6 0x0006
#define PLL_DIV12 0x0007
#define XCLK_SRC_SEL 1
#define MCLK_SRC_SEL 6
#define SCLK_SRC_SEL 1
#define MPLL_CNTL 0
#define VPLL_CNTL 1
#define PLL_REF_DIV 2
#define PLL_GEN_CNTL 3
#define MCLK_FB_DIV 4
#define PLL_GEN_CNTL_MclkScrSel 0x70
#define MCLK_EQU_PLLMCLK_DIV8 0x30
#define MCLK_EQU_SCLK 0x60
#define PLL_VCLK_CNTL 5
#define VCLK_POST_DIV 6
#define VCLK3_FB_DIV 10
#define PLL_EXT_CNTL 11
#define DLL_CNTL 12
#define VFC_CNTL 13
#define SCLK_FB_DIV 21
#define SPLL_CNTL2 23
#define EXT_VPLL_CNTL 25
#define EXT_VPLL_REF_DIV 26
#define EXT_VPLL_FB_DIV 27
#define EXT_VPLL_MSB 28
#define PLL_V2CLK_CNTL 36
#define EXT_V2PLL_REF_DIV 37
#define EXT_V2PLL_FB_DIV 38
#define EXT_V2PLL_MSB 39
#define HTOTAL2_CNTL 40
#define PM_DYN_CLK_CNTL 42
#define PLL_ADDR(p) (((IS_BEDROCK_C(p) == TRUE) || (IS_LT_FAMILY(p) == TRUE)) ? 0x7C : 0x3C)
#define PLL_WR_EN 0x02
#define CLOCK_STROBE 0x40
#define CLOCK_STATUS_RDEN 0x80
#define VPLL_GAIN_CONTROL 0xD5
#define MPLL_GAIN_CONTROL 0xCD
#define MPLL_GAIN_CONTROL_UMC 0xAD
// Text blinking contsants
#define VGA_BLINK_RATE_DEFAULT 16
#define VGA_BLINK_RATE_MIN 16
#define VGA_BLINK_RATE_MAX 32
#define VGA_BLINK_RATE_STEP 16
// Overlay brightness constants
#define OVERLAY_BRIGHTNESS_DEFAULT 0
#define OVERLAY_BRIGHTNESS_MIN -64
#define OVERLAY_BRIGHTNESS_MAX 63
#define OVERLAY_BRIGHTNESS_STEP 1
// Define IDC INF based options
#define DDL_REG_OPTION_LT_USENONEXTPLL4PRIMARY 0x00000010
// Registry value name as must be defined in INF
#define szDDLREGOPTIONLT_USENONEXTPLL4PRIMARY "DDLRegOptionLTUseNonExtPLL4Primary"
#pragma pack()
#endif // _RPROD_H_
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