📄 rprod.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//
// RPROD.H
//
// Copyright (c) 1998 by ATI Technologies Inc.
//
#ifndef _RPROD_H_
#define _RPROD_H_
#pragma pack(1)
//
// *** CHIP FAMILIES ***
//
// Chip family - sorted by growing capability of the chip.
//
enum
{
FAMILY_UNKNOWN = 0,
FAMILY_VTB, // ATI-264VT3 family
FAMILY_VTB_PLUS, // ATI-264VT3 UMC family
FAMILY_VTB_VT4, // ATI-264VT4 family
FAMILY_GTB, // 3D RAGE II family
FAMILY_LTG, // 3D RAGE LT-G family
FAMILY_GTB_PLUS, // 3D RAGE II+ family
FAMILY_GTB_IIC, // 3D RAGE IIC family
FAMILY_GTC, // 3D RAGE PRO family
FAMILY_LT_PRO, // 3D RAGE LT PRO family
FAMILY_RAGE_MOBILITY, // 3D RAGE MOBILITY
FAMILY_RAGE_XL, // 3D RAGE XL
FAMILY_RAGE_XC // 3D RAGE XC
};
#define LTPRO_BIOS_INFO_TABLE_SIGNATURE 0x54504C24 // for '$LPT'
#define RAGEMOBILITY_BIOS_INFO_TABLE_SIGNATURE 0x544D5224 // for '$LPT' changed to "$RMT"
#define RAGEXL_BIOS_INFO_TABLE_SIGNATURE 0x544C5824 // for '$XLT'
#define RAGEXC_BIOS_INFO_TABLE_SIGNATURE 0x54435824 // for '$XCT'
#define FOUR_MEG 0x00400000
#define BIOS_SUPPORTS_SPREAD_SPECTRUM 0x0001
#define BIOS_SUPPORTS_INDEPENDENT_CHANGE_BITS 0x0002
#define BIOS_SUPPORTS_SINGLE_CRTC 0x0004
#define BIOS_SUPPORTS_VERTICAL_BLENDING_DISABLE 0x0008
#define BIOS_SUPPORTS_NO_EXPANSION 0x0010
#define BIOS_SUPPORTS_LCD_ON_OFF_AT_BLANK 0x0020
#define BIOS_SUPPORTS_PARTIAL_POST 0x0040
#define BIOS_SUPPORTS_DYNAMIC_PM 0x0080
// Defines for the DDL get driver options call
#define RPRO_DRIVER_OPTIONS_16BPP_555 0x00000001
#define RPRO_PATCH_FOR_LCD_SYNC_PROBLEM 0x00000002
#define PLL_PROBLEM_N_BLANK_DELAY 0x00000004
#define LT_USE_NON_EXT_PLL_4PRIMARY 0x00000010
// REGISTER: CONFIG_PANEL_DEFAULT
#define CONFIG_PANEL__DEFAULT 0x0f030275
// REGISTER: PL_PLL_CNTL
#define PL_PLL_CNTL_VAL 0x00000a85
//
// *** REGISTERS ***
//
// Define ATI register blocks 1 and 0 as dword offsets from the MM register aperture base.
//
#define ATI_REGISTER_BLOCK1 0x00000000
#define ATI_REGISTER_BLOCK0 0x00000100
//
// Define ATI register selectors as dword offsets from the MM register aperture base.
//
#define CRTC_H_TOTAL_DISP (ATI_REGISTER_BLOCK0 | 0x00)
#define CRTC_H_SYNC_STRT_WID (ATI_REGISTER_BLOCK0 | 0x01)
#define CRTC_V_TOTAL_DISP (ATI_REGISTER_BLOCK0 | 0x02)
#define CRTC_V_SYNC_STRT_WID (ATI_REGISTER_BLOCK0 | 0x03)
#define CRTC_CRNT_VLINE (ATI_REGISTER_BLOCK0 | 0x04)
#define CRTC_OFF_PITCH (ATI_REGISTER_BLOCK0 | 0x05)
#define CRTC_INT_CNTL (ATI_REGISTER_BLOCK0 | 0x06)
#define CRTC_GEN_CNTL (ATI_REGISTER_BLOCK0 | 0x07)
#define DSP_CONFIG (ATI_REGISTER_BLOCK0 | 0x08)
#define DSP_ON_OFF (ATI_REGISTER_BLOCK0 | 0x09)
#define TIMER_CONFIG (ATI_REGISTER_BLOCK0 | 0x0A)
#define MEM_BUF_CNTL (ATI_REGISTER_BLOCK0 | 0x0B)
#define MEM_ADDR_CONFIG (ATI_REGISTER_BLOCK0 | 0x0D)
#define CRT_TRAP (ATI_REGISTER_BLOCK0 | 0x0E)
#define CNTL_0 (ATI_REGISTER_BLOCK0 | 0x0F)
#define OVR_CLR (ATI_REGISTER_BLOCK0 | 0x10)
#define OVR_WID_LEFT_RIGHT (ATI_REGISTER_BLOCK0 | 0x11)
#define OVR_WID_TOP_BOTTOM (ATI_REGISTER_BLOCK0 | 0x12)
#define VGA_DSP_CONFIG (ATI_REGISTER_BLOCK0 | 0x13)
#define VGA_DSP_ON_0FF (ATI_REGISTER_BLOCK0 | 0x14)
#define DSP2_CONFIG (ATI_REGISTER_BLOCK0 | 0x15)
#define DSP2_ON_OFF (ATI_REGISTER_BLOCK0 | 0x16)
#define CRTC2_OFF_PITCH (ATI_REGISTER_BLOCK0 | 0x17)
#define CUR_CLR0 (ATI_REGISTER_BLOCK0 | 0x18)
#define CUR_CLR1 (ATI_REGISTER_BLOCK0 | 0x19)
#define CUR_OFFSET (ATI_REGISTER_BLOCK0 | 0x1A)
#define CUR_HORZ_VERT_POSN (ATI_REGISTER_BLOCK0 | 0x1B)
#define CUR_HORZ_VERT_OFF (ATI_REGISTER_BLOCK0 | 0x1C)
#define TV_OUT_INDEX (ATI_REGISTER_BLOCK0 | 0x1D)
#define GP_IO (ATI_REGISTER_BLOCK0 | 0x1E)
#define HW_DEBUG (ATI_REGISTER_BLOCK0 | 0x1F)
#define SCRATCH_REG0 (ATI_REGISTER_BLOCK0 | 0x20)
#define SCRATCH_REG1 (ATI_REGISTER_BLOCK0 | 0x21)
#define SCRATCH_REG2 (ATI_REGISTER_BLOCK0 | 0x22)
#define SCRATCH_REG3 (ATI_REGISTER_BLOCK0 | 0x23)
#define CLOCK_CNTL (ATI_REGISTER_BLOCK0 | 0x24)
#define CONFIG_STAT1 (ATI_REGISTER_BLOCK0 | 0x25)
#define CONFIG_STAT2 (ATI_REGISTER_BLOCK0 | 0x26)
#define TV_OUT_DATA (ATI_REGISTER_BLOCK0 | 0x27)
#define BUS_CNTL (ATI_REGISTER_BLOCK0 | 0x28)
#define LCD_INDEX (ATI_REGISTER_BLOCK0 | 0x29)
#define LCD_DATA (ATI_REGISTER_BLOCK0 | 0x2A)
#define EXT_MEM_CNTL (ATI_REGISTER_BLOCK0 | 0x2B)
#define MEM_CNTL (ATI_REGISTER_BLOCK0 | 0x2C)
#define MEM_VGA_WP_SEL (ATI_REGISTER_BLOCK0 | 0x2D)
#define MEM_VGA_RP_SEL (ATI_REGISTER_BLOCK0 | 0x2E)
#define LT_GIO (ATI_REGISTER_BLOCK0 | 0x2F)
#define CNTL_1 (ATI_REGISTER_BLOCK0 | 0x2F)
#define DAC_REGS (ATI_REGISTER_BLOCK0 | 0x30)
#define DAC_CNTL (ATI_REGISTER_BLOCK0 | 0x31)
#define EXT_DAC_REGS (ATI_REGISTER_BLOCK0 | 0x32)
#define GEN_TEST_CNTL (ATI_REGISTER_BLOCK0 | 0x34)
#define CUSTOM_MACRO_CNTL (ATI_REGISTER_BLOCK0 | 0x35)
#define CONFIG_CNTL (ATI_REGISTER_BLOCK0 | 0x37)
#define CONFIG_CHIP_ID (ATI_REGISTER_BLOCK0 | 0x38)
#define CONFIG_STAT0 (ATI_REGISTER_BLOCK0 | 0x39)
#define CRC_SIG (ATI_REGISTER_BLOCK0 | 0x3A)
#define OVERLAY_SCALE_CNTL (ATI_REGISTER_BLOCK1 | 0x09)
#define SNAPSHOT_VH_COUNTS (ATI_REGISTER_BLOCK1 | 0x1C)
#define SNAPSHOT_F_COUNT (ATI_REGISTER_BLOCK1 | 0x1D)
#define N_VIF_COUNT (ATI_REGISTER_BLOCK1 | 0x1E)
#define SNAPSHOT_VIF_COUNT (ATI_REGISTER_BLOCK1 | 0x1F)
#define TVO_CNTL (ATI_REGISTER_BLOCK1 | 0x40)
#define CRT_HORIZ_VERT_LOAD (ATI_REGISTER_BLOCK1 | 0x51)
#define SCALER_COLOUR_CNTL (ATI_REGISTER_BLOCK1 | 0x54)
#define GUI_STAT (ATI_REGISTER_BLOCK0 | 0xCE)
// Define VGA sequencer registers.
#define SEQUENCER_INDEX 0x03C4
#define SEQUENCER_DATA 0x03C5
#define SEQUENCER_RESET 0x00
#define SEQUENCER_CLOCK_MODE 0x01
#define SEQUENCER_MAP_MASK 0x02
#define SEQUENCER_CHARACTER_MAP_SELECTOR 0x03
#define SEQUENCER_MEMORY_MODE 0x04
#define SEQUENCER_CLOCK_MODE__SEQ_MAXBW 0x20
// Define 2nd VGA I/O block register selectors as byte offsets from the 2nd VGA I/O register aperture base (0x03C0).
// Comment out this whole block since it is not used in the GCO or GDOs and causes a conflict in Win2K. [cd]
/*
#define VGA_IO2_SEQUENCER_INDEX 0x00000004 // 0x03C4
#define VGA_IO2_SEQUENCER_DATA 0x00000005 // 0x03C5
#define VGA_IO2_DAC_MASK 0x00000006 // 0x03C6
#define VGA_IO2_DAC_WRITE_INDEX 0x00000008 // 0x03C8
#define VGA_IO2_DAC_DATA 0x00000009 // 0x03C9
#define VGA_IO2_GRAPHICS_INDEX 0x0000000E // 0x03CE
#define VGA_IO2_GRAPHICS_DATA 0x0000000F // 0x03CF
*/
// *** MASKS ***
//
// Define masks used with ATI registers.
//
#define CRTC_INT_CNTL_VBlank 0x00000001
#define CRTC_INT_CNTL_VBlankIntEn 0x00000002
#define CRTC_INT_CNTL_VBlankInt 0x00000004
#define CRTC_INT_CNTL_VBlank2 0x00000800
#define CRTC_INT_CNTL_VBlankIntEn2 0x00001000
#define CRTC_INT_CNTL_VBlankInt2 0x00002000
#define CRTC_INT_CNTL_SnapshotIntEn 0x00000080
#define CRTC_INT_CNTL_SnapshotInt 0x00000100
#define CRTC_INT_CNTL_I2CIntEn 0x00000200
#define CRTC_INT_CNTL_I2CInt 0x00000400
#define CRTC_INT_CNTL_Capbuf0IntEn 0x00010000
#define CRTC_INT_CNTL_Capbuf0Int 0x00020000
#define CRTC_INT_CNTL_Capbuf1IntEn 0x00040000
#define CRTC_INT_CNTL_Capbuf1Int 0x00080000
#define CRTC_INT_CNTL_OverlayEofIntEn 0x00100000
#define CRTC_INT_CNTL_OverlayEofInt 0x00200000
#define CRTC_INT_CNTL_OneshotCapIntEn 0x00400000
#define CRTC_INT_CNTL_OneshotCapInt 0x00800000
#define CRTC_INT_CNTL_BusmasterEolIntEn 0x01000000
#define CRTC_INT_CNTL_BusmasterEolInt 0x02000000
#define CRTC_INT_CNTL_GPIntEn 0x04000000
#define CRTC_INT_CNTL_GPInt 0x08000000
#define CRTC_GEN_CNTL_CrtcDblScanEn 0x00000001
#define CRTC_GEN_CNTL_CrtcInterlaceEn 0x00000002
#define CRTC_GEN_CNTL_CrtcCsyncEn 0x00000010
#define CRTC_GEN_CNTL_CrtcMuxModeEn 0x00000020
#define CRTC_GEN_CNTL_Crtc2DblScanEn 0x00000020
#define CRTC_GEN_CNTL_CrtcDisplayDis 0x00000040
#define CRTC_GEN_CNTL_CrtcVgaXoverscan 0x00000080
#define CRTC_GEN_CNTL_CrtcPixWidth 0x00000700
#define CRTC_GEN_CNTL_CrtcExtDispEn 0x01000000
#define CRTC_GEN_CNTL_CrtcEnable 0x02000000
#define CRTC_GEN_CNTL_CrtcLockRegs 0x00400000
#define CRTC2_GEN_CNTL_CrtcPixWidth 0x000E0000
#define CRTC2_GEN_CNTL_CrtcEnable 0x00200000
#define CRTC_GEN_CNTL_Crtc2Enable 0x00200000
#define HW_DEBUG_AutoBlkwrtColorDis 0x00000100
#define HW_DEBUG_AutoFfDis 0x00001000
#define HW_DEBUG_AutoBlkwrtDis 0x00002000
#define LCD_INDEX_RegIndex 0x0000000F
#define LCD_INDEX_LcdDisplayDis 0x00000100
#define LCD_INDEX_LcdSrcSel 0x00000200
#define LCD_INDEX_Crtc2DisplayDis 0x00000400
//Index value for lcd registers
#define LCD_INDEX_ConfigPanelReg 0x00000000
#define LCD_INDEX_lcdGenCtrlReg 0x00000001
#define LCD_INDEX_DstnControl 0x00000002
#define LCD_INDEX_HfbPitchAddr 0x00000003
#define LCD_INDEX_HorzStretching 0x00000004
#define LCD_INDEX_VertStretching 0x00000005
#define LCD_INDEX_ExtVertStretch 0x00000006
#define LCD_INDEX_LtGio 0x00000007
#define LCD_INDEX_PowerManagement 0x00000008
#define LCD_INDEX_LcdMiscCntl 0x00000014
#define LCD_INDEX_Scratch_Pad4 0x00000015
#define LCD_INDEX_PowerManagement2 0x0000001D
#define LCD_INDEX_PLTransmitterCntl 0x00000023
#define LCD_INDEX_PlPllCntl 0x00000024
#define LCD_INDEX_TestIO 0x00000028
#define LCD_INDEX_Scratch_Pad4_PanelID_Mask 0x0000000f
#define TV_OUT_INDEX_TvRgbCntl 0x00000012
#define TV_OUT_INDEX_TvOn 0x00000100
#define TV_RGB_CNTL_RgbSrcSel 0x00000300
#define TV_RGB_CNTL_RgbSrcSelPrm 0x00000000
#define TV_RGB_CNTL_RgbSrcSelPrmExp 0x00000100
#define TV_RGB_CNTL_RgbSrcSelSec 0x00000200
#define LCD_GEN_CTL_CrtcRWSelect 0x08000000
#define LCD_GEN_CTL_LcdShadowEn 0x40000000
#define LCD_GEN_CTL_ShadowRWEnable 0x80000000
#define LCD_GEN_CTL_CrtOn 0x00000001
#define LCD_GEN_CTL_LcdOn 0x00000002
#define LCD_GEN_CTL_HorzDivby2En 0x00000004
#define LCD_GEN_CTL_DontShadowVpar 0x00000040
#define LCD_GEN_CTL_DisHorCrtDivBy2 0x00000400
#define LCD_GEN_CTL_UseShadowedVend 0x10000000
#define HFB_PITCH_ADDR_CrtSyncSel 0x00010000
#define HFB_PITCH_ADDR_XbufSize 0x00000F00
#define HORZ_STRETCHING_AutoHorzRatio 0x20000000
#define HORZ_STRETCHING_HorzStretchMode 0x40000000
#define HORZ_STRETCHING_HorzStretchEn 0x80000000
#define VERT_STRETCHING_UseRatio0 0x40000000
#define VERT_STRETCHING_VertStretchEn 0x80000000
#define EXT_VERT_STRETCH_VertSrtchMode 0x00000400
#define EXT_VERT_STRETCH_AutoVertRatio 0x00400000
#define EXT_VERT_STRETCH_UseAutoFpPos 0x00800000
#define POWER_MANAGEMENT_2_PmDynXclkSyncMask 0x00003000 // Mask to set synchronization condition
#define POWER_MANAGEMENT_2_PmDynXclkSyncPrmDis 0x00000000 // Start of VBLANK on primary display
#define POWER_MANAGEMENT_2_PmDynXclkEn 0x00010000 // Enables dynamic XCLK power saving mode
#define POWER_MANAGEMENT_2_PmDynXclkDisp 0x00100000 // Enables Slower XCLK when Primary display is active
#define CLOCK_CNTL_ClockSel 0x00000003
#define CLOCK_CNTL_PllWrEn 0x00000200
#define CLOCK_CNTL_PllAddr 0x00007C00
#define CLOCK_CNTL_PllAddrBit5 0x00008000
#define DSP_CONFIG_DspFlushWb 0x00008000
#define DSP2_CONFIG_DspFlushWb 0x00008000
#define MEM_CNTL_MemSize 0x0000000F
#define MEM_CNTL_MemLatency 0x00000030
#define MEM_CNTL_MemTrp 0x00000300
#define MEM_CNTL_MemTrcd 0x00000C00
#define MEM_CNTL_MemTcrd 0x00001000
#define MEM_CNTL_MemTras 0x00070000
#define DAC_CNTL_DacCmpDisable 0x00000008
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