📄 main7.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk305:in std_logic;
coo:out std_logic);
end;
architecture a of fenpin is
signal p:integer range 0 to 4;
begin
process(clk305)
begin
if clk305'event and clk305='1' then
if p=4 then
p<=0;
else
p<=p+1;
end if;
end if;
if p<=2 then
coo<='1';
else
coo<='0';
end if;
end process;
end;
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity mod80 is
port(clk1:in std_logic;
dout:out std_logic_vector(1 downto 0 )
);
end ;
architecture modba of mod80 is
signal qq:std_logic_vector(1 downto 0);
begin
process(clk1) is
begin
if(clk1'event and clk1='1') then
if(qq="11")then
qq<="00";
else
qq<=qq+1;
end if;
end if;
dout<=qq;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity decoder7 is
port(in2:in std_logic_vector(1 downto 0);
out7:out std_logic_vector(1 to 7)
);
end ;
architecture ade of decoder7 is
begin
process(in2) is
begin
case in2 is
when "01"=>out7<="0110000";
when "10"=>out7<="1101101";
when "11"=>out7<="1111001";
when others =>out7<="0000000";
end case;
end process;
end architecture;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity keytest is
port (clk,up1,up2,down2,down3,key1,key2,key3,tiqian,yanshi: in std_logic;
f1_up,f2_down,f2_up,f3_down,ddoor: out std_logic;
up_down:buffer std_logic;-- ke yi inout?
current:out std_logic_vector(1 downto 0));
end keytest;
architecture test1 of keytest is
type state_type is (c1,c2,c3,close_d,close_d1,time3,time4);
begin
process(clk)
variable u,ting: std_logic_vector(3 downto 1):="000";
variable state:state_type:=c1;
variable qcnt2:integer range 0 to 300;
variable f1,f2,f3,ti,ya,d2:std_logic;
begin
if clk'event and clk='1' then
if up1='0' then
u(1):='1';
f1_up<='1';
end if;--
if up2='0' then
u(2):='1';
f2_up<='1';
end if;
if down2='0' then
d2:='1';
f2_down<='1';
end if;
if down3='0' then
u(3):='1';
f3_down<='1';
end if;--
if key1='0' then
ting(1):='1';
end if;--
if key2='0' then
ting(2):='1';
end if;--
if key3='0' then
ting(3):='1';
end if;--
if tiqian='0' then
ti:='1';
end if;
if yanshi='0' then
ya:='1';
end if;
case state is
when time4 =>
ddoor<='1';
if ti='1' then
qcnt2:=201;
ti:='0';
elsif ya='1' then
qcnt2:=0;
ya:='0';
end if;
if qcnt2<200 then
qcnt2:=qcnt2+1;
else
qcnt2:=0;
state:=close_d1;
end if ;
when time3=>
ddoor<='0';
if qcnt2<200 then
qcnt2:=qcnt2+1;
else
qcnt2:=0;
if f1='1' then
state:=c2;
elsif f2='1' then
if up_down='1' and ting(3)='1' then
state:=c3;
elsif up_down='0' and ting(1)='1' then
state:=c1;
elsif up_down='1' and u(3)='1' then
state:=c3;
elsif up_down='0' and u(1)='1' then
state:=c1;
elsif u(1)='1' or ting(1)='1' then
state:=c1;
UP_DOWN<='0';
elsif u(3)='1' or ting(3)='1' then
state:=c3;
UP_DOWN='1';
end if;
elsif f3='1' then
state:=c2;
end if;
end if;
when c1=>
current<="01";
up_down<='1';
f2:='0';
f3:='0';
f1:='0';
f1_up<='0';
if u(1)='1' or ting(1)='1' then
f1:='1';
u(1):='0';
ting(1):='0';
state:=time4;
elsif u(2)='1' or ting(2)='1' or u(3)='1' or ting(3)='1' or d2='1' then
f1:='1' ;
state:=time3;
end if;
when c2=>
f2_up<='0';
f2_down<='0';
f1:='0';
f2:='0';
f3:='0';
current<="10";
if up_down='1' and u(2)='1' then
u(2):='0';
f2:='1';
state:=time4;
elsif up_down='0' and d2='1' then
d2:='0';
f2:='1';
state:=time4;
elsif ting(1)='1' and up_down='0' then
f2:='1' ;
state:=time3;
elsif ting(3)='1' and up_down='1' then
f2:='1';
state:=time3;
elsif u(1)='1' and up_down='0' then
f2:='1';
state:=time3;
elsif u(3)='1' and up_down='1' then
f2:='1';
state:=time3;
elsif u(1)='1' or ting(1)='1' then
f2:='1';
up_down<='0';
state:=time3;
elsif ting(3)='1' or u(3)='1' then
f2:='1' ;
up_down<='1';
state:=time3;
end if;
when c3=>
current<="11";
up_down<='0';
f3_down<='0';
f1:='0';
f2:='0';
f3:='0';
if u(3)='1' or ting(3)='1' then
f3:='1';
u(3):='0';
ting(3):='0';
state:=time4;
elsif u(1)='1' or u(2)='1' or ting(1)='1' or ting(2)='1' or d2='1' then
f3:='1';
state:=time3;
end if;
when close_d1=>
ddoor<='0';
if f1='1' then
current<="01";
f1_up<='0';
if u(1)='1' then
u(1):='0';
up_down<='1';
state:=time4;
else
state:=close_d;
end if;
elsif f2='1' then
current<="10";
f2_up<='0';
f2_down<='0';
if u(2)='1' then
u(2):='0';
up_down<='1';
state:=time4;
elsif d2='1' then
d2:='0';
up_down<='0';
state:=time4;
else
state:=close_d;
end if;
elsif f3='1' then
current<="11";
f3_down<='0';
if u(3)='1' then
u(3):='0';
state:=time4;
else
state:=close_d;
end if;
end if;
when close_d=>
ddoor<='0';
if f1='1' then
current<="01";
f1_up<='0';
if u(2)='1' or d2='1' or ting(2)='1' or u(3)='1' or ting(3)='1' then
up_down<='1';
state:=time3;
else
state:=close_d1;
end if;
elsif f2='1' then
current<="10";
f2_up<='0';
f2_down<='0';
if ting(1)='1' and up_down='0' then
up_down<='0';
state:=time3;
elsif ting(3)='1' and up_down='1' then
up_down<='1';
state:=time3;
elsif u(1)='1' and up_down='0' then
up_down<='0';
state:=time3;
elsif u(3)='1' and up_down='1' then
up_down<='1';
state:=time3;
elsif u(1)='1' or ting(1)='1' then
up_down<='0';--
state:=time3;--
elsif u(3)='1' or ting(3)='1' then
up_down<='1';
state:=time3;
else
state:=close_d1;
end if;
elsif f3='1' then
current<="11";
f3_down<='0';
if u(2)='1' or d2='1'or ting(2)='1' or u(1)='1' or ting(1)='1' then
up_down<='0';
state:=time3;
else
state:=close_d1;
end if;
end if;
when others => null;
end case;
end if;--clk
end process;
end architecture test1;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity main7 is
port(clk,up1,up2,down2,down3,key1,key2,key3,eary,delay:in std_logic;
f1_up,f2_down,f2_up,f3_down,gate:out std_logic;
up_down:buffer std_logic;-- ke yi inout ?
sel:out std_logic_vector(1 downto 0 );
out7:out std_logic_vector(1 to 7)
);
end entity main7;
architecture mar of main7 is
component fenpin is
port(clk305:in std_logic;
coo:out std_logic);
end component fenpin;
component mod80 is
port(clk1:in std_logic;
dout:out std_logic_vector(1 downto 0 )
);
end component mod80;
component decoder7 is
port(in2:in std_logic_vector(1 downto 0);
out7:out std_logic_vector(1 to 7)
);
end component decoder7;
component keytest is
port (clk,up1,up2,down2,down3,key1,key2,key3,tiqian,yanshi: in std_logic;
f1_up,f2_down,f2_up,f3_down,ddoor: out std_logic;
up_down:buffer std_logic;-- ke yi inout?
current:out std_logic_vector(1 downto 0));
end component keytest;
signal clk100:std_logic;
signal ks:std_logic_vector(1 downto 0);
begin
unit1: fenpin port map(clk,clk100);
unit2: decoder7 port map(ks,out7);
unit3: keytest port map(clk100,up1,up2,down2,down3,key1,key2,key3,eary,delay,f1_up,f2_down,f2_up,f3_down,gate,up_down,ks);
unit4: mod80 port map(clk,sel);
end architecture mar;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -