set_pll.c

基于ADI blackfin处理器的范例程序

/********************************************************************************/
/***** Set_PLL(CoreCLOCK_multiplier, SCLK_divider)							*****/
/***** Sets core and system clock 											*****/
/********************************************************************************/

// only MSEL and SSEL supported at this time
// no checks for invalid or out of range settings

#include "system.h"


void Set_PLL(short CoreCLOCK_multiplier, short SCLK_divider)
{ short previous_PLL= *pPLL_CTL;
  short previous_SIC_IWR = *pSIC_IWR;
  short new_PLL= (previous_PLL & 0x81ff) | ((CoreCLOCK_multiplier & 0x3f) <<9);
   
  if (new_PLL != previous_PLL) {			  // skip if multiplier has not changed
		  	
	*pSIC_IWR = (previous_SIC_IWR | 0x1); // enable PLL Wakeup Interrupt
	*pPLL_CTL = new_PLL;
	ssync();
  		
 	idle();							  // put in idle

 	*pSIC_IWR = previous_SIC_IWR;		  // continue here after idle, restore previous IWR content
	ssync();
		
  }   // if (new_PLL != previous_PLL)

  *pPLL_DIV = (*pPLL_DIV & 0xFFF8) | SCLK_divider;
  ssync();
  
}