📄 bsc_ber.mdl
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MaxIdLength 31
PreserveName off
PreserveNameWithParent off
ShowEliminatedStatement off
IncAutoGenComments off
SimulinkDataObjDesc off
SFDataObjDesc off
IncDataTypeInIds off
PrefixModelToSubsysFcnNames on
MangleLength 1
CustomSymbolStrGlobalVar "$R$N$M"
CustomSymbolStrType "$N$R$M"
CustomSymbolStrField "$N$M"
CustomSymbolStrFcn "$R$N$M$F"
CustomSymbolStrBlkIO "rtb_$N$M"
CustomSymbolStrTmpVar "$N$M"
CustomSymbolStrMacro "$R$N$M"
DefineNamingRule "None"
ParamNamingRule "None"
SignalNamingRule "None"
InsertBlockDesc off
SimulinkBlockComments on
EnableCustomComments off
InlinedPrmAccess "Literals"
ReqsInCode off
}
Simulink.GRTTargetCC {
$BackupClass "Simulink.TargetCC"
$ObjectID 10
Array {
Type "Cell"
Dimension 13
Cell "IncludeMdlTerminateFcn"
Cell "CombineOutputUpdateFcns"
Cell "SuppressErrorStatus"
Cell "ERTCustomFileBanners"
Cell "GenerateSampleERTMain"
Cell "GenerateTestInterfaces"
Cell "MultiInstanceERTCode"
Cell "PurelyIntegerCode"
Cell "SupportNonFinite"
Cell "SupportComplex"
Cell "SupportAbsoluteTime"
Cell "SupportContinuousTime"
Cell "SupportNonInlinedSFcns"
PropName "DisabledProps"
}
Version "1.2.0"
TargetFcnLib "ansi_tfl_tmw.mat"
TargetLibSuffix ""
TargetPreCompLibLocation ""
GenFloatMathFcnCalls "ANSI_C"
UtilityFuncGeneration "Auto"
GenerateFullHeader on
GenerateSampleERTMain off
GenerateTestInterfaces off
IsPILTarget off
ModelReferenceCompliant on
IncludeMdlTerminateFcn on
CombineOutputUpdateFcns off
SuppressErrorStatus off
IncludeFileDelimiter "Auto"
ERTCustomFileBanners off
SupportAbsoluteTime on
LogVarNameModifier "rt_"
MatFileLogging on
MultiInstanceERTCode off
SupportNonFinite on
SupportComplex on
PurelyIntegerCode off
SupportContinuousTime on
SupportNonInlinedSFcns on
EnableShiftOperators on
ParenthesesLevel "Nominal"
ExtMode off
ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
RTWCAPIStates off
GenerateASAP2 off
}
PropName "Components"
}
}
hdlcoderui.hdlcc {
$ObjectID 11
Description "HDL Coder custom configuration component"
Version "1.2.0"
Name "HDL Coder"
Array {
Type "Cell"
Dimension 1
Cell ""
PropName "HDLConfigFile"
}
HDLCActiveTab "0"
}
PropName "Components"
}
Name "Configuration"
SimulationMode "normal"
CurrentDlgPage "Solver"
}
PropName "ConfigurationSets"
}
Simulink.ConfigSet {
$PropName "ActiveConfigurationSet"
$ObjectID 1
}
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
BlockParameterDefaults {
Block {
BlockType Constant
}
Block {
BlockType FrameConversion
OutFrame "Frame based"
}
Block {
BlockType Inport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
IconShape "rectangular"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType RelationalOperator
Operator ">="
InputSameDT on
LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Reshape
OutputDimensionality "1-D array"
OutputDimensions "[1,1]"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Terminator
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "BSC_BER"
Location [213, 122, 793, 415]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
ShowPageBoundaries off
ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Bernoulli Binary\nGenerator"
Ports [0, 1]
Position [30, 58, 110, 102]
DialogController "commDDGCreate"
DialogControllerArgs "DataTag0"
FontName "Arial"
SourceBlock "commrandsrc2/Bernoulli Binary\nGenerator"
SourceType "Bernoulli Binary Generator"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
P "0.5"
seed "61"
Ts "xSampleTime"
frameBased off
sampPerFrame "1"
orient off
outDataType "double"
}
Block {
BlockType Reference
Name "Binary Symmetric\nChannel"
Ports [1, 1]
Position [190, 50, 285, 110]
SourceBlock "commchan3/Binary Symmetric\nChannel"
SourceType "Binary Symmetric Channel"
ShowPortLabels on
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
P "BitErrorRate"
s "71"
E off
outDtype "double"
}
Block {
BlockType Reference
Name "Error Rate\nCalculation"
Ports [2]
Position [375, 192, 450, 243]
SourceBlock "commsink2/Error Rate\nCalculation"
SourceType "Error Rate Calculation"
N "0"
st_delay "0"
cp_mode "Entire frame"
subframe "[]"
PMode "Workspace"
WsName "xErrorRate"
RsMode2 off
stop off
numErr "100"
maxBits "1e6"
}
Line {
SrcBlock "Binary Symmetric\nChannel"
SrcPort 1
Points [35, 0; 0, 125]
DstBlock "Error Rate\nCalculation"
DstPort 1
}
Line {
SrcBlock "Bernoulli Binary\nGenerator"
SrcPort 1
Points [30, 0]
Branch {
DstBlock "Binary Symmetric\nChannel"
DstPort 1
}
Branch {
Points [0, 150]
DstBlock "Error Rate\nCalculation"
DstPort 2
}
}
Annotation {
Position [125, 84]
UseDisplayTextAsClickCallback off
}
}
}
MatData {
NumRecords 1
DataRecord {
Tag DataTag0
Data " %)30 . > 8 ( 0 % "
"\" $ ! 0 . 2 8 ( ! % \" $ "
"2 0 0 $@ $)E<FYO=6QL:4)I;F%R>4=E;@ "
}
}
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