decode.map.qmsg

来自「在射频识别RFID芯片设计中用到的miller解码器设计」· QMSG 代码 · 共 15 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 12 16:07:44 2005 " "Info: Processing started: Tue Jul 12 16:07:44 2005" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off decode -c decode " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decode -c decode" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "decode.v(101) " "Warning (10268): Verilog HDL information at decode.v(101): Always Construct contains both blocking and non-blocking assignments" {  } { { "../decode.v" "" { Text "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/decode.v" 101 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../decode.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 decode " "Info: Found entity 1: decode" {  } { { "../decode.v" "" { Text "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/decode.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "decode " "Info: Elaborating entity \"decode\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "current_flag decode.v(101) " "Warning (10240): Verilog HDL Always Construct warning at decode.v(101): inferring latch(es) for variable \"current_flag\", which holds its previous value in one or more paths through the always construct" {  } { { "../decode.v" "" { Text "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/decode.v" 101 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_flag\[1\] decode.v(21) " "Info (10041): Verilog HDL or VHDL info at decode.v(21): inferred latch for \"current_flag\[1\]\"" {  } { { "../decode.v" "" { Text "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/decode.v" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "current_flag\[0\] decode.v(21) " "Info (10041): Verilog HDL or VHDL info at decode.v(21): inferred latch for \"current_flag\[0\]\"" {  } { { "../decode.v" "" { Text "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/decode.v" 21 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Error" "EVRFX_VRFC_NET_MULTIPLE_DRIVERS" "current_flag\[1\] decode.v(56) " "Error (10028): Can't resolve multiple constant drivers for net \"current_flag\[1\]\" at decode.v(56)" {  } { { "../decode.v" "" { Text "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/decode.v" 56 0 0 } }  } 0 10028 "Can't resolve multiple constant drivers for net \"%1!s!\" at %2!s!" 0 0}
{ "Error" "EVRFX_VRFC_NET_ANOTHER_DRIVER" "decode.v(21) " "Error (10029): Constant driver at decode.v(21)" {  } { { "../decode.v" "" { Text "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/decode.v" 21 0 0 } }  } 0 10029 "Constant driver at %1!s!" 0 0}
{ "Error" "ESGN_TOP_HIER_ELABORATION_FAILURE" "" "Error: Can't elaborate top-level user hierarchy" {  } {  } 0 0 "Can't elaborate top-level user hierarchy" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_BANNER_TIME" "Tue Jul 12 16:07:45 2005 " "Error: Processing ended: Tue Jul 12 16:07:45 2005" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/miller解码器设计/decode.map.smsg " "Info: Generated suppressed messages file E:/钟伟的资料/RFID-SOC/编解码模块/miller解码器设计(050710)/源代码/miller解码器设计/decode.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}