📄 mcg.lst
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\ mcg_blpi_2_pee:
\ 00000000 80B5 PUSH {R7,LR}
185 uint8 temp_reg;
186 // Transition from BLPI to PEE: BLPI -> FBI -> FEI -> FBE -> PBE -> PEE
187
188 // Step 1: BLPI -> FBI
189 MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
\ 00000002 .... LDR.N R0,??DataTable3 ;; 0x40064001
\ 00000004 0078 LDRB R0,[R0, #+0]
\ 00000006 10F0FD00 ANDS R0,R0,#0xFD
\ 0000000A .... LDR.N R1,??DataTable3 ;; 0x40064001
\ 0000000C 0870 STRB R0,[R1, #+0]
190 while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.
\ ??mcg_blpi_2_pee_0:
\ 0000000E .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 00000010 0078 LDRB R0,[R0, #+0]
\ 00000012 C006 LSLS R0,R0,#+27
\ 00000014 FBD5 BPL.N ??mcg_blpi_2_pee_0
191 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update
\ ??mcg_blpi_2_pee_1:
\ 00000016 .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 00000018 0078 LDRB R0,[R0, #+0]
\ 0000001A C0F38100 UBFX R0,R0,#+2,#+2
\ 0000001E C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000020 0128 CMP R0,#+1
\ 00000022 F8D1 BNE.N ??mcg_blpi_2_pee_1
192
193 // Step 2: FBI -> FEI
194 MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
\ 00000024 .... LDR.N R0,??DataTable3 ;; 0x40064001
\ 00000026 0078 LDRB R0,[R0, #+0]
\ 00000028 10F0FD00 ANDS R0,R0,#0xFD
\ 0000002C .... LDR.N R1,??DataTable3 ;; 0x40064001
\ 0000002E 0870 STRB R0,[R1, #+0]
195 temp_reg = MCG_C2; // assign temporary variable of MCG_C2 contents
\ 00000030 .... LDR.N R0,??DataTable3 ;; 0x40064001
\ 00000032 0078 LDRB R0,[R0, #+0]
196 temp_reg &= ~MCG_C2_RANGE_MASK; // set RANGE field location to zero
\ 00000034 10F0CF00 ANDS R0,R0,#0xCF
197 temp_reg |= (0x2 << 0x4); // OR in new values
\ 00000038 50F02000 ORRS R0,R0,#0x20
198 MCG_C2 = temp_reg; // store new value in MCG_C2
\ 0000003C .... LDR.N R1,??DataTable3 ;; 0x40064001
\ 0000003E 0870 STRB R0,[R1, #+0]
199 MCG_C4 = 0x0E; // Low-range DCO output (~10MHz bus). FCTRIM=%0111.
\ 00000040 .... LDR.N R0,??DataTable3_7 ;; 0x40064003
\ 00000042 0E21 MOVS R1,#+14
\ 00000044 0170 STRB R1,[R0, #+0]
200 MCG_C1 = 0x04; // Select internal clock as MCG source, FRDIV=%000, internal reference selected.
\ 00000046 .... LDR.N R0,??DataTable3_3 ;; 0x40064000
\ 00000048 0421 MOVS R1,#+4
\ 0000004A 0170 STRB R1,[R0, #+0]
201
202 while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update
\ ??mcg_blpi_2_pee_2:
\ 0000004C .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 0000004E 0078 LDRB R0,[R0, #+0]
\ 00000050 C006 LSLS R0,R0,#+27
\ 00000052 FBD5 BPL.N ??mcg_blpi_2_pee_2
203 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x0){}; // Wait for clock status bits to update
\ ??mcg_blpi_2_pee_3:
\ 00000054 .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 00000056 0078 LDRB R0,[R0, #+0]
\ 00000058 C0F38100 UBFX R0,R0,#+2,#+2
\ 0000005C C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 0000005E 0028 CMP R0,#+0
\ 00000060 F8D1 BNE.N ??mcg_blpi_2_pee_3
204
205 // Handle FEI to PEE transitions using standard clock initialization routine.
206 core_clk_mhz = pll_init(CORE_CLK_MHZ, REF_CLK);
\ 00000062 0321 MOVS R1,#+3
\ 00000064 0220 MOVS R0,#+2
\ 00000066 ........ BL pll_init
\ 0000006A .... LDR.N R1,??DataTable3_8
\ 0000006C 0860 STR R0,[R1, #+0]
207
208 /* Use the value obtained from the pll_init function to define variables
209 * for the core clock in kHz and also the peripheral clock. These
210 * variables can be used by other functions that need awareness of the
211 * system frequency.
212 */
213 core_clk_khz = core_clk_mhz * 1000;
\ 0000006E .... LDR.N R0,??DataTable3_8
\ 00000070 0068 LDR R0,[R0, #+0]
\ 00000072 4FF47A71 MOV R1,#+1000
\ 00000076 4843 MULS R0,R1,R0
\ 00000078 .... LDR.N R1,??DataTable3_9
\ 0000007A 0860 STR R0,[R1, #+0]
214 periph_clk_khz = core_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);
\ 0000007C .... LDR.N R0,??DataTable3_9
\ 0000007E 0068 LDR R0,[R0, #+0]
\ 00000080 .... LDR.N R1,??DataTable3_10 ;; 0x40048044
\ 00000082 0968 LDR R1,[R1, #+0]
\ 00000084 C1F30361 UBFX R1,R1,#+24,#+4
\ 00000088 491C ADDS R1,R1,#+1
\ 0000008A B0FBF1F0 UDIV R0,R0,R1
\ 0000008E .... LDR.N R1,??DataTable3_11
\ 00000090 0860 STR R0,[R1, #+0]
215 } // end MCG BLPI to PEE
\ 00000092 01BD POP {R0,PC} ;; return
216 /********************************************************************/
217
\ In section .text, align 2, keep-with-next
218 void mcg_pbe_2_pee(void)
219 {
220 MCG_C1 &= ~MCG_C1_CLKS_MASK; // select PLL as MCG_OUT
\ mcg_pbe_2_pee:
\ 00000000 .... LDR.N R0,??DataTable3_3 ;; 0x40064000
\ 00000002 0078 LDRB R0,[R0, #+0]
\ 00000004 10F03F00 ANDS R0,R0,#0x3F
\ 00000008 .... LDR.N R1,??DataTable3_3 ;; 0x40064000
\ 0000000A 0870 STRB R0,[R1, #+0]
221 // Wait for clock status bits to update
222 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
\ ??mcg_pbe_2_pee_0:
\ 0000000C .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 0000000E 0078 LDRB R0,[R0, #+0]
\ 00000010 C0F38100 UBFX R0,R0,#+2,#+2
\ 00000014 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000016 0328 CMP R0,#+3
\ 00000018 F8D1 BNE.N ??mcg_pbe_2_pee_0
223
224 switch (CORE_CLK_MHZ) {
225 case PLL50:
226 core_clk_khz = 50000;
227 break;
228 case PLL100:
229 core_clk_khz = 100000;
230 break;
231 case PLL96:
232 core_clk_khz = 96000;
\ 0000001A .... LDR.N R0,??DataTable3_9
\ 0000001C .... LDR.N R1,??DataTable3_12 ;; 0x17700
\ 0000001E 0160 STR R1,[R0, #+0]
233 break;
234 case PLL48:
235 core_clk_khz = 48000;
236 break;
237 }
238 }
\ 00000020 7047 BX LR ;; return
\ In section .text, align 4, keep-with-next
\ ??DataTable3:
\ 00000000 01400640 DC32 0x40064001
\ In section .text, align 4, keep-with-next
\ ??DataTable3_1:
\ 00000000 34800440 DC32 0x40048034
\ In section .text, align 4, keep-with-next
\ ??DataTable3_2:
\ 00000000 08C00740 DC32 0x4007c008
\ In section .text, align 4, keep-with-next
\ ??DataTable3_3:
\ 00000000 00400640 DC32 0x40064000
\ In section .text, align 4, keep-with-next
\ ??DataTable3_4:
\ 00000000 06400640 DC32 0x40064006
\ In section .text, align 4, keep-with-next
\ ??DataTable3_5:
\ 00000000 04400640 DC32 0x40064004
\ In section .text, align 4, keep-with-next
\ ??DataTable3_6:
\ 00000000 05400640 DC32 0x40064005
\ In section .text, align 4, keep-with-next
\ ??DataTable3_7:
\ 00000000 03400640 DC32 0x40064003
\ In section .text, align 4, keep-with-next
\ ??DataTable3_8:
\ 00000000 ........ DC32 core_clk_mhz
\ In section .text, align 4, keep-with-next
\ ??DataTable3_9:
\ 00000000 ........ DC32 core_clk_khz
\ In section .text, align 4, keep-with-next
\ ??DataTable3_10:
\ 00000000 44800440 DC32 0x40048044
\ In section .text, align 4, keep-with-next
\ ??DataTable3_11:
\ 00000000 ........ DC32 periph_clk_khz
\ In section .text, align 4, keep-with-next
\ ??DataTable3_12:
\ 00000000 00770100 DC32 0x17700
Maximum stack usage in bytes:
Function .cstack
-------- -------
mcg_blpi_2_pee 8
mcg_pbe_2_pee 0
mcg_pee_2_blpi 0
pll_init 8
set_sys_dividers 12
Section sizes:
Function/Label Bytes
-------------- -----
pll_init 246
set_sys_dividers 76
mcg_pee_2_blpi 156
mcg_blpi_2_pee 148
mcg_pbe_2_pee 34
??DataTable3 4
??DataTable3_1 4
??DataTable3_2 4
??DataTable3_3 4
??DataTable3_4 4
??DataTable3_5 4
??DataTable3_6 4
??DataTable3_7 4
??DataTable3_8 4
??DataTable3_9 4
??DataTable3_10 4
??DataTable3_11 4
??DataTable3_12 4
636 bytes in section .text
76 bytes in section .textrw
712 bytes of CODE memory
Errors: none
Warnings: none
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