📄 mcg.lst
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###############################################################################
# #
# IAR ANSI C/C++ Compiler V6.10.1.52143/W32 for ARM 16/Apr/2011 16:44:06 #
# Copyright 1999-2010 IAR Systems AB. #
# #
# Cpu mode = thumb #
# Endian = little #
# Source file = E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\drivers\mcg\mcg.c #
# Command line = "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\drivers\mcg\mcg.c" -D IAR #
# -D TWR_K60N512 -lCN "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\bin\Flash\List\" -lB #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\bin\Flash\List\" -o #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\bin\Flash\Obj\" --no_cse #
# --no_unroll --no_inline --no_code_motion --no_tbaa #
# --no_clustering --no_scheduling --debug --endian=little #
# --cpu=Cortex-M4 -e --fpu=None --dlib_config #
# D:\iar\arm\INC\c\DLib_Config_Normal.h -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\common\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\cpu\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\cpu\headers\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\drivers\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\drivers\uart\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\drivers\gpio\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\drivers\mcg\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\drivers\wdog\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\projects\" -I #
# "E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\src\" -Ol --use_c++_inline #
# List file = E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\bin\Flash\List\mcg.lst #
# Object file = E:\Project\15_K60\03_Software\02_My #
# program\K60_IAR\01_light\bin\Flash\Obj\mcg.o #
# #
# #
###############################################################################
E:\Project\15_K60\03_Software\02_My program\K60_IAR\01_light\src\drivers\mcg\mcg.c
1 /*
2 * File: mcg.c
3 * Purpose: Driver for enabling the PLL in 1 of 4 options
4 *
5 * Notes:
6 * Assumes the MCG mode is in the default FEI mode out of reset
7 * One of 4 clocking oprions can be selected.
8 * One of 16 crystal values can be used
9 */
10
11 #include "common.h"
12 #include "mcg.h"
13
14 extern int core_clk_khz;
15 extern int core_clk_mhz;
16 extern int periph_clk_khz;
17
\ In section .text, align 2, keep-with-next
18 unsigned char pll_init(unsigned char clk_option, unsigned char crystal_val)
19 {
\ pll_init:
\ 00000000 80B5 PUSH {R7,LR}
\ 00000002 0A00 MOVS R2,R1
20 unsigned char pll_freq;
21
22 if (clk_option > 3) {return 0;} //return 0 if one of the available options is not selected
\ 00000004 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000006 0428 CMP R0,#+4
\ 00000008 01D3 BCC.N ??pll_init_0
\ 0000000A 0020 MOVS R0,#+0
\ 0000000C 72E0 B.N ??pll_init_1
23 if (crystal_val > 15) {return 1;} // return 1 if one of the available crystal options is not available
\ ??pll_init_0:
\ 0000000E D2B2 UXTB R2,R2 ;; ZeroExt R2,R2,#+24,#+24
\ 00000010 102A CMP R2,#+16
\ 00000012 01D3 BCC.N ??pll_init_2
\ 00000014 0120 MOVS R0,#+1
\ 00000016 6DE0 B.N ??pll_init_1
24 //This assumes that the MCG is in default FEI mode out of reset.
25
26 // First move to FBE mode
27 #if (defined(K60_CLK) || defined(ASB817))
28 MCG_C2 = 0;
\ ??pll_init_2:
\ 00000018 .... LDR.N R2,??DataTable3 ;; 0x40064001
\ 0000001A 0023 MOVS R3,#+0
\ 0000001C 1370 STRB R3,[R2, #+0]
29 #else
30 // Enable external oscillator, RANGE=2, HGO=1, EREFS=1, LP=0, IRCS=0
31 MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
32 #endif
33
34 // after initialization of oscillator release latched state of oscillator and GPIO
35 SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
\ 0000001E .... LDR.N R2,??DataTable3_1 ;; 0x40048034
\ 00000020 1268 LDR R2,[R2, #+0]
\ 00000022 52F08052 ORRS R2,R2,#0x10000000
\ 00000026 .... LDR.N R3,??DataTable3_1 ;; 0x40048034
\ 00000028 1A60 STR R2,[R3, #+0]
36 LLWU_CS |= LLWU_CS_ACKISO_MASK;
\ 0000002A .... LDR.N R2,??DataTable3_2 ;; 0x4007c008
\ 0000002C 1278 LDRB R2,[R2, #+0]
\ 0000002E 52F08002 ORRS R2,R2,#0x80
\ 00000032 .... LDR.N R3,??DataTable3_2 ;; 0x4007c008
\ 00000034 1A70 STRB R2,[R3, #+0]
37
38 // Select external oscilator and Reference Divider and clear IREFS to start ext osc
39 // CLKS=2, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
40 MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
\ 00000036 .... LDR.N R2,??DataTable3_3 ;; 0x40064000
\ 00000038 9823 MOVS R3,#+152
\ 0000003A 1370 STRB R3,[R2, #+0]
41
42 /* if we aren't using an osc input we don't need to wait for the osc to init */
43 #if (!defined(K60_CLK) && !defined(ASB817))
44 while (!(MCG_S & MCG_S_OSCINIT_MASK)){}; // wait for oscillator to initialize
45 #endif
46
47 while (MCG_S & MCG_S_IREFST_MASK){}; // wait for Reference clock Status bit to clear
\ ??pll_init_3:
\ 0000003C .... LDR.N R2,??DataTable3_4 ;; 0x40064006
\ 0000003E 1278 LDRB R2,[R2, #+0]
\ 00000040 D206 LSLS R2,R2,#+27
\ 00000042 FBD4 BMI.N ??pll_init_3
48
49 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status bits to show clock source is ext ref clk
\ ??pll_init_4:
\ 00000044 .... LDR.N R2,??DataTable3_4 ;; 0x40064006
\ 00000046 1278 LDRB R2,[R2, #+0]
\ 00000048 C2F38102 UBFX R2,R2,#+2,#+2
\ 0000004C D2B2 UXTB R2,R2 ;; ZeroExt R2,R2,#+24,#+24
\ 0000004E 022A CMP R2,#+2
\ 00000050 F8D1 BNE.N ??pll_init_4
50
51 // Now in FBE
52
53 #if (defined(K60_CLK))
54 MCG_C5 = MCG_C5_PRDIV(0x18);
\ 00000052 .... LDR.N R2,??DataTable3_5 ;; 0x40064004
\ 00000054 1823 MOVS R3,#+24
\ 00000056 1370 STRB R3,[R2, #+0]
55 #else
56 // Configure PLL Ref Divider, PLLCLKEN=0, PLLSTEN=0, PRDIV=5
57 // The crystal frequency is used to select the PRDIV value. Only even frequency crystals are supported
58 // that will produce a 2MHz reference clock to the PLL.
59 MCG_C5 = MCG_C5_PRDIV(crystal_val); // Set PLL ref divider to match the crystal used
60 #endif
61
62 // Ensure MCG_C6 is at the reset default of 0. LOLIE disabled, PLL disabled, clk monitor disabled, PLL VCO divider is clear
63 MCG_C6 = 0x0;
\ 00000058 .... LDR.N R2,??DataTable3_6 ;; 0x40064005
\ 0000005A 0023 MOVS R3,#+0
\ 0000005C 1370 STRB R3,[R2, #+0]
64 // Select the PLL VCO divider and system clock dividers depending on clocking option
65 switch (clk_option) {
\ 0000005E C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000060 0028 CMP R0,#+0
\ 00000062 05D0 BEQ.N ??pll_init_5
\ 00000064 0228 CMP R0,#+2
\ 00000066 19D0 BEQ.N ??pll_init_6
\ 00000068 0DD3 BCC.N ??pll_init_7
\ 0000006A 0328 CMP R0,#+3
\ 0000006C 21D0 BEQ.N ??pll_init_8
\ 0000006E 2AE0 B.N ??pll_init_9
66 case 0:
67 // Set system options dividers
68 //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
69 set_sys_dividers(0,0,0,1);
\ ??pll_init_5:
\ 00000070 0123 MOVS R3,#+1
\ 00000072 0022 MOVS R2,#+0
\ 00000074 0021 MOVS R1,#+0
\ 00000076 0020 MOVS R0,#+0
\ 00000078 ........ BL set_sys_dividers
70 // Set the VCO divider and enable the PLL for 50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
71 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
\ 0000007C .... LDR.N R0,??DataTable3_6 ;; 0x40064005
\ 0000007E 4121 MOVS R1,#+65
\ 00000080 0170 STRB R1,[R0, #+0]
72 pll_freq = 50;
\ 00000082 3221 MOVS R1,#+50
73 break;
\ 00000084 1FE0 B.N ??pll_init_9
74 case 1:
75 // Set system options dividers
76 //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
77 set_sys_dividers(0,1,1,3);
\ ??pll_init_7:
\ 00000086 0323 MOVS R3,#+3
\ 00000088 0122 MOVS R2,#+1
\ 0000008A 0121 MOVS R1,#+1
\ 0000008C 0020 MOVS R0,#+0
\ 0000008E ........ BL set_sys_dividers
78 // Set the VCO divider and enable the PLL for 100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
79 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
\ 00000092 .... LDR.N R0,??DataTable3_6 ;; 0x40064005
\ 00000094 5A21 MOVS R1,#+90
\ 00000096 0170 STRB R1,[R0, #+0]
80 pll_freq = 100;
\ 00000098 6421 MOVS R1,#+100
81 break;
\ 0000009A 14E0 B.N ??pll_init_9
82 case 2:
83 // Set system options dividers
84 //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
85 set_sys_dividers(0,1,1,3);
\ ??pll_init_6:
\ 0000009C 0323 MOVS R3,#+3
\ 0000009E 0122 MOVS R2,#+1
\ 000000A0 0121 MOVS R1,#+1
\ 000000A2 0020 MOVS R0,#+0
\ 000000A4 ........ BL set_sys_dividers
86 // Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
87 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
\ 000000A8 .... LDR.N R0,??DataTable3_6 ;; 0x40064005
\ 000000AA 5821 MOVS R1,#+88
\ 000000AC 0170 STRB R1,[R0, #+0]
88 pll_freq = 96;
\ 000000AE 6021 MOVS R1,#+96
89 break;
\ 000000B0 09E0 B.N ??pll_init_9
90 case 3:
91 // Set system options dividers
92 //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
93 set_sys_dividers(0,0,0,1);
\ ??pll_init_8:
\ 000000B2 0123 MOVS R3,#+1
\ 000000B4 0022 MOVS R2,#+0
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