📄 mcg.s
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??set_sys_dividers_2:
ADDS R0,R0,#+1
??set_sys_dividers_1:
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,R3
BCC.N ??set_sys_dividers_2
// 142 {}
// 143
// 144 FMC_PFAPR = temp_reg; // re-store original value of FMC_PFAPR
LDR.N R0,??set_sys_dividers_0 ;; 0x4001f000
STR R4,[R0, #+0]
// 145
// 146 return;
POP {R4-R6}
BX LR ;; return
DATA
??set_sys_dividers_0:
DC32 0x4001f000
DC32 0x40048044
// 147 } // set_sys_dividers
// 148
// 149
// 150 /********************************************************************/
SECTION `.text`:CODE:NOROOT(1)
THUMB
// 151 void mcg_pee_2_blpi(void)
// 152 {
// 153 uint8 temp_reg;
// 154 // Transition from PEE to BLPI: PEE -> PBE -> FBE -> FBI -> BLPI
// 155
// 156 // Step 1: PEE -> PBE
// 157 MCG_C1 |= MCG_C1_CLKS(2); // System clock from external reference OSC, not PLL.
mcg_pee_2_blpi:
LDR.N R0,??DataTable3_3 ;; 0x40064000
LDRB R0,[R0, #+0]
ORRS R0,R0,#0x80
LDR.N R1,??DataTable3_3 ;; 0x40064000
STRB R0,[R1, #+0]
// 158 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status to update.
??mcg_pee_2_blpi_0:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
UBFX R0,R0,#+2,#+2
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,#+2
BNE.N ??mcg_pee_2_blpi_0
// 159
// 160 // Step 2: PBE -> FBE
// 161 MCG_C6 &= ~MCG_C6_PLLS_MASK; // Clear PLLS to select FLL, still running system from ext OSC.
LDR.N R0,??DataTable3_6 ;; 0x40064005
LDRB R0,[R0, #+0]
ANDS R0,R0,#0xBF
LDR.N R1,??DataTable3_6 ;; 0x40064005
STRB R0,[R1, #+0]
// 162 while (MCG_S & MCG_S_PLLST_MASK){}; // Wait for PLL status flag to reflect FLL selected.
??mcg_pee_2_blpi_1:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
LSLS R0,R0,#+26
BMI.N ??mcg_pee_2_blpi_1
// 163
// 164 // Step 3: FBE -> FBI
// 165 MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
LDR.N R0,??DataTable3 ;; 0x40064001
LDRB R0,[R0, #+0]
ANDS R0,R0,#0xFD
LDR.N R1,??DataTable3 ;; 0x40064001
STRB R0,[R1, #+0]
// 166 MCG_C2 |= MCG_C2_IRCS_MASK; // Select fast (1MHz) internal reference
LDR.N R0,??DataTable3 ;; 0x40064001
LDRB R0,[R0, #+0]
ORRS R0,R0,#0x1
LDR.N R1,??DataTable3 ;; 0x40064001
STRB R0,[R1, #+0]
// 167 temp_reg = MCG_C1;
LDR.N R0,??DataTable3_3 ;; 0x40064000
LDRB R0,[R0, #+0]
// 168 temp_reg &= ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK);
ANDS R0,R0,#0x3B
// 169 temp_reg |= (MCG_C1_CLKS(1) | MCG_C1_IREFS_MASK); // Select internal reference (fast IREF clock @ 1MHz) as MCG clock source.
ORRS R0,R0,#0x44
// 170 MCG_C1 = temp_reg;
LDR.N R1,??DataTable3_3 ;; 0x40064000
STRB R0,[R1, #+0]
// 171
// 172 while (MCG_S & MCG_S_IREFST_MASK){}; // Wait for Reference Status bit to update.
??mcg_pee_2_blpi_2:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
LSLS R0,R0,#+27
BMI.N ??mcg_pee_2_blpi_2
// 173 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update
??mcg_pee_2_blpi_3:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
UBFX R0,R0,#+2,#+2
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,#+1
BNE.N ??mcg_pee_2_blpi_3
// 174
// 175 // Step 4: FBI -> BLPI
// 176 MCG_C1 |= MCG_C1_IREFSTEN_MASK; // Keep internal reference clock running in STOP modes.
LDR.N R0,??DataTable3_3 ;; 0x40064000
LDRB R0,[R0, #+0]
ORRS R0,R0,#0x1
LDR.N R1,??DataTable3_3 ;; 0x40064000
STRB R0,[R1, #+0]
// 177 MCG_C2 |= MCG_C2_LP_MASK; // FLL remains disabled in bypassed modes.
LDR.N R0,??DataTable3 ;; 0x40064001
LDRB R0,[R0, #+0]
ORRS R0,R0,#0x2
LDR.N R1,??DataTable3 ;; 0x40064001
STRB R0,[R1, #+0]
// 178 while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.
??mcg_pee_2_blpi_4:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
LSLS R0,R0,#+27
BPL.N ??mcg_pee_2_blpi_4
// 179 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update.
??mcg_pee_2_blpi_5:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
UBFX R0,R0,#+2,#+2
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,#+1
BNE.N ??mcg_pee_2_blpi_5
// 180
// 181 } // end MCG PEE to BLPI
BX LR ;; return
// 182 /********************************************************************/
SECTION `.text`:CODE:NOROOT(1)
THUMB
// 183 void mcg_blpi_2_pee(void)
// 184 {
mcg_blpi_2_pee:
PUSH {R7,LR}
// 185 uint8 temp_reg;
// 186 // Transition from BLPI to PEE: BLPI -> FBI -> FEI -> FBE -> PBE -> PEE
// 187
// 188 // Step 1: BLPI -> FBI
// 189 MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
LDR.N R0,??DataTable3 ;; 0x40064001
LDRB R0,[R0, #+0]
ANDS R0,R0,#0xFD
LDR.N R1,??DataTable3 ;; 0x40064001
STRB R0,[R1, #+0]
// 190 while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.
??mcg_blpi_2_pee_0:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
LSLS R0,R0,#+27
BPL.N ??mcg_blpi_2_pee_0
// 191 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update
??mcg_blpi_2_pee_1:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
UBFX R0,R0,#+2,#+2
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,#+1
BNE.N ??mcg_blpi_2_pee_1
// 192
// 193 // Step 2: FBI -> FEI
// 194 MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
LDR.N R0,??DataTable3 ;; 0x40064001
LDRB R0,[R0, #+0]
ANDS R0,R0,#0xFD
LDR.N R1,??DataTable3 ;; 0x40064001
STRB R0,[R1, #+0]
// 195 temp_reg = MCG_C2; // assign temporary variable of MCG_C2 contents
LDR.N R0,??DataTable3 ;; 0x40064001
LDRB R0,[R0, #+0]
// 196 temp_reg &= ~MCG_C2_RANGE_MASK; // set RANGE field location to zero
ANDS R0,R0,#0xCF
// 197 temp_reg |= (0x2 << 0x4); // OR in new values
ORRS R0,R0,#0x20
// 198 MCG_C2 = temp_reg; // store new value in MCG_C2
LDR.N R1,??DataTable3 ;; 0x40064001
STRB R0,[R1, #+0]
// 199 MCG_C4 = 0x0E; // Low-range DCO output (~10MHz bus). FCTRIM=%0111.
LDR.N R0,??DataTable3_7 ;; 0x40064003
MOVS R1,#+14
STRB R1,[R0, #+0]
// 200 MCG_C1 = 0x04; // Select internal clock as MCG source, FRDIV=%000, internal reference selected.
LDR.N R0,??DataTable3_3 ;; 0x40064000
MOVS R1,#+4
STRB R1,[R0, #+0]
// 201
// 202 while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update
??mcg_blpi_2_pee_2:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
LSLS R0,R0,#+27
BPL.N ??mcg_blpi_2_pee_2
// 203 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x0){}; // Wait for clock status bits to update
??mcg_blpi_2_pee_3:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
UBFX R0,R0,#+2,#+2
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,#+0
BNE.N ??mcg_blpi_2_pee_3
// 204
// 205 // Handle FEI to PEE transitions using standard clock initialization routine.
// 206 core_clk_mhz = pll_init(CORE_CLK_MHZ, REF_CLK);
MOVS R1,#+3
MOVS R0,#+2
BL pll_init
LDR.N R1,??DataTable3_8
STR R0,[R1, #+0]
// 207
// 208 /* Use the value obtained from the pll_init function to define variables
// 209 * for the core clock in kHz and also the peripheral clock. These
// 210 * variables can be used by other functions that need awareness of the
// 211 * system frequency.
// 212 */
// 213 core_clk_khz = core_clk_mhz * 1000;
LDR.N R0,??DataTable3_8
LDR R0,[R0, #+0]
MOV R1,#+1000
MULS R0,R1,R0
LDR.N R1,??DataTable3_9
STR R0,[R1, #+0]
// 214 periph_clk_khz = core_clk_khz / (((SIM_CLKDIV1 & SIM_CLKDIV1_OUTDIV2_MASK) >> 24)+ 1);
LDR.N R0,??DataTable3_9
LDR R0,[R0, #+0]
LDR.N R1,??DataTable3_10 ;; 0x40048044
LDR R1,[R1, #+0]
UBFX R1,R1,#+24,#+4
ADDS R1,R1,#+1
UDIV R0,R0,R1
LDR.N R1,??DataTable3_11
STR R0,[R1, #+0]
// 215 } // end MCG BLPI to PEE
POP {R0,PC} ;; return
// 216 /********************************************************************/
// 217
SECTION `.text`:CODE:NOROOT(1)
THUMB
// 218 void mcg_pbe_2_pee(void)
// 219 {
// 220 MCG_C1 &= ~MCG_C1_CLKS_MASK; // select PLL as MCG_OUT
mcg_pbe_2_pee:
LDR.N R0,??DataTable3_3 ;; 0x40064000
LDRB R0,[R0, #+0]
ANDS R0,R0,#0x3F
LDR.N R1,??DataTable3_3 ;; 0x40064000
STRB R0,[R1, #+0]
// 221 // Wait for clock status bits to update
// 222 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
??mcg_pbe_2_pee_0:
LDR.N R0,??DataTable3_4 ;; 0x40064006
LDRB R0,[R0, #+0]
UBFX R0,R0,#+2,#+2
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,#+3
BNE.N ??mcg_pbe_2_pee_0
// 223
// 224 switch (CORE_CLK_MHZ) {
// 225 case PLL50:
// 226 core_clk_khz = 50000;
// 227 break;
// 228 case PLL100:
// 229 core_clk_khz = 100000;
// 230 break;
// 231 case PLL96:
// 232 core_clk_khz = 96000;
LDR.N R0,??DataTable3_9
LDR.N R1,??DataTable3_12 ;; 0x17700
STR R1,[R0, #+0]
// 233 break;
// 234 case PLL48:
// 235 core_clk_khz = 48000;
// 236 break;
// 237 }
// 238 }
BX LR ;; return
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3:
DC32 0x40064001
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_1:
DC32 0x40048034
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_2:
DC32 0x4007c008
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_3:
DC32 0x40064000
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_4:
DC32 0x40064006
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_5:
DC32 0x40064004
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_6:
DC32 0x40064005
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_7:
DC32 0x40064003
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_8:
DC32 core_clk_mhz
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_9:
DC32 core_clk_khz
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_10:
DC32 0x40048044
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_11:
DC32 periph_clk_khz
SECTION `.text`:CODE:NOROOT(2)
DATA
??DataTable3_12:
DC32 0x17700
SECTION __DLIB_PERTHREAD:DATA:REORDER:NOROOT(0)
SECTION __DLIB_PERTHREAD_init:DATA:REORDER:NOROOT(0)
END
//
// 636 bytes in section .text
// 76 bytes in section .textrw
//
// 712 bytes of CODE memory
//
//Errors: none
//Warnings: none
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