📄 sysinit.lst
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\ 0000000E D2B2 UXTB R2,R2 ;; ZeroExt R2,R2,#+24,#+24
\ 00000010 102A CMP R2,#+16
\ 00000012 01D3 BCC.N ??pll_init_2
\ 00000014 0120 MOVS R0,#+1
\ 00000016 6DE0 B.N ??pll_init_1
85
86 //这里处在默认的FEI模式
87 //首先移动到FBE模式
88 #if (defined(K60_CLK) || defined(ASB817))
89 MCG_C2 = 0;
\ ??pll_init_2:
\ 00000018 .... LDR.N R2,??DataTable3_9 ;; 0x40064001
\ 0000001A 0023 MOVS R3,#+0
\ 0000001C 1370 STRB R3,[R2, #+0]
90 #else
91 //使能外部晶振
92 MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
93 #endif
94
95 //初始化晶振后释放锁定状态的振荡器和GPIO
96 SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
\ 0000001E .... LDR.N R2,??DataTable3_10 ;; 0x40048034
\ 00000020 1268 LDR R2,[R2, #+0]
\ 00000022 52F08052 ORRS R2,R2,#0x10000000
\ 00000026 .... LDR.N R3,??DataTable3_10 ;; 0x40048034
\ 00000028 1A60 STR R2,[R3, #+0]
97 LLWU_CS |= LLWU_CS_ACKISO_MASK;
\ 0000002A .... LDR.N R2,??DataTable3_11 ;; 0x4007c008
\ 0000002C 1278 LDRB R2,[R2, #+0]
\ 0000002E 52F08002 ORRS R2,R2,#0x80
\ 00000032 .... LDR.N R3,??DataTable3_11 ;; 0x4007c008
\ 00000034 1A70 STRB R2,[R3, #+0]
98
99 //选择外部晶振，参考分频器，清IREFS来启动外部晶振
100 MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
\ 00000036 .... LDR.N R2,??DataTable3_12 ;; 0x40064000
\ 00000038 9823 MOVS R3,#+152
\ 0000003A 1370 STRB R3,[R2, #+0]
101
102 //等待晶振稳定
103 #if (!defined(K60_CLK) && !defined(ASB817))
104 while (!(MCG_S & MCG_S_OSCINIT_MASK)){};
105 #endif
106
107 //等待参考时钟状态位清零
108 while (MCG_S & MCG_S_IREFST_MASK){};
\ ??pll_init_3:
\ 0000003C .... LDR.N R2,??DataTable3_13 ;; 0x40064006
\ 0000003E 1278 LDRB R2,[R2, #+0]
\ 00000040 D206 LSLS R2,R2,#+27
\ 00000042 FBD4 BMI.N ??pll_init_3
109 //等待时钟状态位显示时钟源来自外部参考时钟
110 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){};
\ ??pll_init_4:
\ 00000044 .... LDR.N R2,??DataTable3_13 ;; 0x40064006
\ 00000046 1278 LDRB R2,[R2, #+0]
\ 00000048 C2F38102 UBFX R2,R2,#+2,#+2
\ 0000004C D2B2 UXTB R2,R2 ;; ZeroExt R2,R2,#+24,#+24
\ 0000004E 022A CMP R2,#+2
\ 00000050 F8D1 BNE.N ??pll_init_4
111
112 //进入FBE模式
113 #if (defined(K60_CLK))
114 MCG_C5 = MCG_C5_PRDIV(0x18);
\ 00000052 .... LDR.N R2,??DataTable3_14 ;; 0x40064004
\ 00000054 1823 MOVS R3,#+24
\ 00000056 1370 STRB R3,[R2, #+0]
115 #else
116
117 //配置PLL分频器来匹配所用的晶振
118 MCG_C5 = MCG_C5_PRDIV(crystal_val);
119 #endif
120
121 //确保MCG_C6处于复位状态，禁止LOLIE、PLL、和时钟控制器，清PLL VCO分频器
122 MCG_C6 = 0x0;
\ 00000058 .... LDR.N R2,??DataTable3_15 ;; 0x40064005
\ 0000005A 0023 MOVS R3,#+0
\ 0000005C 1370 STRB R3,[R2, #+0]
123 //选择PLL VCO分频器，系统时钟分频器取决于时钟选项
124 switch (clk_option) {
\ 0000005E C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000060 0028 CMP R0,#+0
\ 00000062 05D0 BEQ.N ??pll_init_5
\ 00000064 0228 CMP R0,#+2
\ 00000066 19D0 BEQ.N ??pll_init_6
\ 00000068 0DD3 BCC.N ??pll_init_7
\ 0000006A 0328 CMP R0,#+3
\ 0000006C 21D0 BEQ.N ??pll_init_8
\ 0000006E 2AE0 B.N ??pll_init_9
125 case 0:
126 //设置系统分频器
127 //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
128 set_sys_dividers(0,0,0,1);
\ ??pll_init_5:
\ 00000070 0123 MOVS R3,#+1
\ 00000072 0022 MOVS R2,#+0
\ 00000074 0021 MOVS R1,#+0
\ 00000076 0020 MOVS R0,#+0
\ 00000078 ........ BL set_sys_dividers
129 //设置VCO分频器，使能PLL为50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
130 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
\ 0000007C .... LDR.N R0,??DataTable3_15 ;; 0x40064005
\ 0000007E 4121 MOVS R1,#+65
\ 00000080 0170 STRB R1,[R0, #+0]
131 pll_freq = 50;
\ 00000082 3221 MOVS R1,#+50
132 break;
\ 00000084 1FE0 B.N ??pll_init_9
133 case 1:
134 //设置系统分频器
135 //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
136 set_sys_dividers(0,1,1,3);
\ ??pll_init_7:
\ 00000086 0323 MOVS R3,#+3
\ 00000088 0122 MOVS R2,#+1
\ 0000008A 0121 MOVS R1,#+1
\ 0000008C 0020 MOVS R0,#+0
\ 0000008E ........ BL set_sys_dividers
137 //设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
138 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
\ 00000092 .... LDR.N R0,??DataTable3_15 ;; 0x40064005
\ 00000094 5A21 MOVS R1,#+90
\ 00000096 0170 STRB R1,[R0, #+0]
139 pll_freq = 100;
\ 00000098 6421 MOVS R1,#+100
140 break;
\ 0000009A 14E0 B.N ??pll_init_9
141 case 2:
142 //设置系统分频器
143 //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
144 set_sys_dividers(0,1,1,3);
\ ??pll_init_6:
\ 0000009C 0323 MOVS R3,#+3
\ 0000009E 0122 MOVS R2,#+1
\ 000000A0 0121 MOVS R1,#+1
\ 000000A2 0020 MOVS R0,#+0
\ 000000A4 ........ BL set_sys_dividers
145 //设置VCO分频器，使能PLL为96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
146 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
\ 000000A8 .... LDR.N R0,??DataTable3_15 ;; 0x40064005
\ 000000AA 5821 MOVS R1,#+88
\ 000000AC 0170 STRB R1,[R0, #+0]
147 pll_freq = 96;
\ 000000AE 6021 MOVS R1,#+96
148 break;
\ 000000B0 09E0 B.N ??pll_init_9
149 case 3:
150 //设置系统分频器
151 //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
152 set_sys_dividers(0,0,0,1);
\ ??pll_init_8:
\ 000000B2 0123 MOVS R3,#+1
\ 000000B4 0022 MOVS R2,#+0
\ 000000B6 0021 MOVS R1,#+0
\ 000000B8 0020 MOVS R0,#+0
\ 000000BA ........ BL set_sys_dividers
153 //设置VCO分频器，使能PLL为48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
154 MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
\ 000000BE .... LDR.N R0,??DataTable3_15 ;; 0x40064005
\ 000000C0 4021 MOVS R1,#+64
\ 000000C2 0170 STRB R1,[R0, #+0]
155 pll_freq = 48;
\ 000000C4 3021 MOVS R1,#+48
156 break;
157 }
158 while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
\ ??pll_init_9:
\ 000000C6 .... LDR.N R0,??DataTable3_13 ;; 0x40064006
\ 000000C8 0078 LDRB R0,[R0, #+0]
\ 000000CA 8006 LSLS R0,R0,#+26
\ 000000CC FBD5 BPL.N ??pll_init_9
159
160 while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
\ ??pll_init_10:
\ 000000CE .... LDR.N R0,??DataTable3_13 ;; 0x40064006
\ 000000D0 0078 LDRB R0,[R0, #+0]
\ 000000D2 4006 LSLS R0,R0,#+25
\ 000000D4 FBD5 BPL.N ??pll_init_10
161
162 //进入PBE模式
163
164 //通过清零CLKS位来进入PEE模式
165 // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
166 MCG_C1 &= ~MCG_C1_CLKS_MASK;
\ 000000D6 .... LDR.N R0,??DataTable3_12 ;; 0x40064000
\ 000000D8 0078 LDRB R0,[R0, #+0]
\ 000000DA 10F03F00 ANDS R0,R0,#0x3F
\ 000000DE .... LDR.N R2,??DataTable3_12 ;; 0x40064000
\ 000000E0 1070 STRB R0,[R2, #+0]
167
168 //等待时钟状态位更新
169 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
\ ??pll_init_11:
\ 000000E2 .... LDR.N R0,??DataTable3_13 ;; 0x40064006
\ 000000E4 0078 LDRB R0,[R0, #+0]
\ 000000E6 C0F38100 UBFX R0,R0,#+2,#+2
\ 000000EA C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 000000EC 0328 CMP R0,#+3
\ 000000EE F8D1 BNE.N ??pll_init_11
170
171 //开始进入PEE模式
172
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