📄 mcg.lst
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\ 000000B6 0021 MOVS R1,#+0
\ 000000B8 0020 MOVS R0,#+0
\ 000000BA ........ BL set_sys_dividers
94 // Set the VCO divider and enable the PLL for 48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
95 MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
\ 000000BE .... LDR.N R0,??DataTable3_6 ;; 0x40064005
\ 000000C0 4021 MOVS R1,#+64
\ 000000C2 0170 STRB R1,[R0, #+0]
96 pll_freq = 48;
\ 000000C4 3021 MOVS R1,#+48
97 break;
98 }
99 while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
\ ??pll_init_9:
\ 000000C6 .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 000000C8 0078 LDRB R0,[R0, #+0]
\ 000000CA 8006 LSLS R0,R0,#+26
\ 000000CC FBD5 BPL.N ??pll_init_9
100
101 while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
\ ??pll_init_10:
\ 000000CE .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 000000D0 0078 LDRB R0,[R0, #+0]
\ 000000D2 4006 LSLS R0,R0,#+25
\ 000000D4 FBD5 BPL.N ??pll_init_10
102
103 // Now running PBE Mode
104
105 // Transition into PEE by setting CLKS to 0
106 // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
107 MCG_C1 &= ~MCG_C1_CLKS_MASK;
\ 000000D6 .... LDR.N R0,??DataTable3_3 ;; 0x40064000
\ 000000D8 0078 LDRB R0,[R0, #+0]
\ 000000DA 10F03F00 ANDS R0,R0,#0x3F
\ 000000DE .... LDR.N R2,??DataTable3_3 ;; 0x40064000
\ 000000E0 1070 STRB R0,[R2, #+0]
108
109 // Wait for clock status bits to update
110 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
\ ??pll_init_11:
\ 000000E2 .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 000000E4 0078 LDRB R0,[R0, #+0]
\ 000000E6 C0F38100 UBFX R0,R0,#+2,#+2
\ 000000EA C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 000000EC 0328 CMP R0,#+3
\ 000000EE F8D1 BNE.N ??pll_init_11
111
112 // Now running PEE Mode
113
114 return pll_freq;
\ 000000F0 0800 MOVS R0,R1
\ 000000F2 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ ??pll_init_1:
\ 000000F4 02BD POP {R1,PC} ;; return
115 } //pll_init
116
\ In section .textrw, align 4, keep-with-next
117 __ramfunc void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4)
118 {
\ set_sys_dividers:
\ 00000000 70B4 PUSH {R4-R6}
119 /*
120 * This routine must be placed in RAM. It is a workaround for errata e2448.
121 * Flash prefetch must be disabled when the flash clock divider is changed.
122 * This cannot be performed while executing out of flash.
123 * There must be a short delay after the clock dividers are changed before prefetch
124 * can be re-enabled.
125 */
126 uint32 temp_reg;
127 uint8 i;
128
129 temp_reg = FMC_PFAPR; // store present value of FMC_PFAPR
\ 00000002 104C LDR.N R4,??set_sys_dividers_0 ;; 0x4001f000
\ 00000004 2468 LDR R4,[R4, #+0]
130
131 // set M0PFD through M7PFD to 1 to disable prefetch
132 FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK | FMC_PFAPR_M5PFD_MASK
133 | FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK
134 | FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;
\ 00000006 0F4D LDR.N R5,??set_sys_dividers_0 ;; 0x4001f000
\ 00000008 2D68 LDR R5,[R5, #+0]
\ 0000000A 55F47F05 ORRS R5,R5,#0xFF0000
\ 0000000E 0D4E LDR.N R6,??set_sys_dividers_0 ;; 0x4001f000
\ 00000010 3560 STR R5,[R6, #+0]
135
136 // set clock dividers to desired value
137 SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2)
138 | SIM_CLKDIV1_OUTDIV3(outdiv3) | SIM_CLKDIV1_OUTDIV4(outdiv4);
\ 00000012 0906 LSLS R1,R1,#+24
\ 00000014 11F07061 ANDS R1,R1,#0xF000000
\ 00000018 51EA0070 ORRS R0,R1,R0, LSL #+28
\ 0000001C 1105 LSLS R1,R2,#+20
\ 0000001E 11F47001 ANDS R1,R1,#0xF00000
\ 00000022 0843 ORRS R0,R1,R0
\ 00000024 1904 LSLS R1,R3,#+16
\ 00000026 11F47021 ANDS R1,R1,#0xF0000
\ 0000002A 0843 ORRS R0,R1,R0
\ 0000002C 0649 LDR.N R1,??set_sys_dividers_0+0x4 ;; 0x40048044
\ 0000002E 0860 STR R0,[R1, #+0]
139
140 // wait for dividers to change
141 for (i = 0 ; i < outdiv4 ; i++)
\ 00000030 0020 MOVS R0,#+0
\ 00000032 00E0 B.N ??set_sys_dividers_1
\ ??set_sys_dividers_2:
\ 00000034 401C ADDS R0,R0,#+1
\ ??set_sys_dividers_1:
\ 00000036 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000038 9842 CMP R0,R3
\ 0000003A FBD3 BCC.N ??set_sys_dividers_2
142 {}
143
144 FMC_PFAPR = temp_reg; // re-store original value of FMC_PFAPR
\ 0000003C 0148 LDR.N R0,??set_sys_dividers_0 ;; 0x4001f000
\ 0000003E 0460 STR R4,[R0, #+0]
145
146 return;
\ 00000040 70BC POP {R4-R6}
\ 00000042 7047 BX LR ;; return
\ ??set_sys_dividers_0:
\ 00000044 00F00140 DC32 0x4001f000
\ 00000048 44800440 DC32 0x40048044
147 } // set_sys_dividers
148
149
150 /********************************************************************/
\ In section .text, align 2, keep-with-next
151 void mcg_pee_2_blpi(void)
152 {
153 uint8 temp_reg;
154 // Transition from PEE to BLPI: PEE -> PBE -> FBE -> FBI -> BLPI
155
156 // Step 1: PEE -> PBE
157 MCG_C1 |= MCG_C1_CLKS(2); // System clock from external reference OSC, not PLL.
\ mcg_pee_2_blpi:
\ 00000000 .... LDR.N R0,??DataTable3_3 ;; 0x40064000
\ 00000002 0078 LDRB R0,[R0, #+0]
\ 00000004 50F08000 ORRS R0,R0,#0x80
\ 00000008 .... LDR.N R1,??DataTable3_3 ;; 0x40064000
\ 0000000A 0870 STRB R0,[R1, #+0]
158 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}; // Wait for clock status to update.
\ ??mcg_pee_2_blpi_0:
\ 0000000C .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 0000000E 0078 LDRB R0,[R0, #+0]
\ 00000010 C0F38100 UBFX R0,R0,#+2,#+2
\ 00000014 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000016 0228 CMP R0,#+2
\ 00000018 F8D1 BNE.N ??mcg_pee_2_blpi_0
159
160 // Step 2: PBE -> FBE
161 MCG_C6 &= ~MCG_C6_PLLS_MASK; // Clear PLLS to select FLL, still running system from ext OSC.
\ 0000001A .... LDR.N R0,??DataTable3_6 ;; 0x40064005
\ 0000001C 0078 LDRB R0,[R0, #+0]
\ 0000001E 10F0BF00 ANDS R0,R0,#0xBF
\ 00000022 .... LDR.N R1,??DataTable3_6 ;; 0x40064005
\ 00000024 0870 STRB R0,[R1, #+0]
162 while (MCG_S & MCG_S_PLLST_MASK){}; // Wait for PLL status flag to reflect FLL selected.
\ ??mcg_pee_2_blpi_1:
\ 00000026 .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 00000028 0078 LDRB R0,[R0, #+0]
\ 0000002A 8006 LSLS R0,R0,#+26
\ 0000002C FBD4 BMI.N ??mcg_pee_2_blpi_1
163
164 // Step 3: FBE -> FBI
165 MCG_C2 &= ~MCG_C2_LP_MASK; // FLL remains active in bypassed modes.
\ 0000002E .... LDR.N R0,??DataTable3 ;; 0x40064001
\ 00000030 0078 LDRB R0,[R0, #+0]
\ 00000032 10F0FD00 ANDS R0,R0,#0xFD
\ 00000036 .... LDR.N R1,??DataTable3 ;; 0x40064001
\ 00000038 0870 STRB R0,[R1, #+0]
166 MCG_C2 |= MCG_C2_IRCS_MASK; // Select fast (1MHz) internal reference
\ 0000003A .... LDR.N R0,??DataTable3 ;; 0x40064001
\ 0000003C 0078 LDRB R0,[R0, #+0]
\ 0000003E 50F00100 ORRS R0,R0,#0x1
\ 00000042 .... LDR.N R1,??DataTable3 ;; 0x40064001
\ 00000044 0870 STRB R0,[R1, #+0]
167 temp_reg = MCG_C1;
\ 00000046 .... LDR.N R0,??DataTable3_3 ;; 0x40064000
\ 00000048 0078 LDRB R0,[R0, #+0]
168 temp_reg &= ~(MCG_C1_CLKS_MASK | MCG_C1_IREFS_MASK);
\ 0000004A 10F03B00 ANDS R0,R0,#0x3B
169 temp_reg |= (MCG_C1_CLKS(1) | MCG_C1_IREFS_MASK); // Select internal reference (fast IREF clock @ 1MHz) as MCG clock source.
\ 0000004E 50F04400 ORRS R0,R0,#0x44
170 MCG_C1 = temp_reg;
\ 00000052 .... LDR.N R1,??DataTable3_3 ;; 0x40064000
\ 00000054 0870 STRB R0,[R1, #+0]
171
172 while (MCG_S & MCG_S_IREFST_MASK){}; // Wait for Reference Status bit to update.
\ ??mcg_pee_2_blpi_2:
\ 00000056 .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 00000058 0078 LDRB R0,[R0, #+0]
\ 0000005A C006 LSLS R0,R0,#+27
\ 0000005C FBD4 BMI.N ??mcg_pee_2_blpi_2
173 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update
\ ??mcg_pee_2_blpi_3:
\ 0000005E .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 00000060 0078 LDRB R0,[R0, #+0]
\ 00000062 C0F38100 UBFX R0,R0,#+2,#+2
\ 00000066 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000068 0128 CMP R0,#+1
\ 0000006A F8D1 BNE.N ??mcg_pee_2_blpi_3
174
175 // Step 4: FBI -> BLPI
176 MCG_C1 |= MCG_C1_IREFSTEN_MASK; // Keep internal reference clock running in STOP modes.
\ 0000006C .... LDR.N R0,??DataTable3_3 ;; 0x40064000
\ 0000006E 0078 LDRB R0,[R0, #+0]
\ 00000070 50F00100 ORRS R0,R0,#0x1
\ 00000074 .... LDR.N R1,??DataTable3_3 ;; 0x40064000
\ 00000076 0870 STRB R0,[R1, #+0]
177 MCG_C2 |= MCG_C2_LP_MASK; // FLL remains disabled in bypassed modes.
\ 00000078 .... LDR.N R0,??DataTable3 ;; 0x40064001
\ 0000007A 0078 LDRB R0,[R0, #+0]
\ 0000007C 50F00200 ORRS R0,R0,#0x2
\ 00000080 .... LDR.N R1,??DataTable3 ;; 0x40064001
\ 00000082 0870 STRB R0,[R1, #+0]
178 while (!(MCG_S & MCG_S_IREFST_MASK)){}; // Wait for Reference Status bit to update.
\ ??mcg_pee_2_blpi_4:
\ 00000084 .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 00000086 0078 LDRB R0,[R0, #+0]
\ 00000088 C006 LSLS R0,R0,#+27
\ 0000008A FBD5 BPL.N ??mcg_pee_2_blpi_4
179 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x1){}; // Wait for clock status bits to update.
\ ??mcg_pee_2_blpi_5:
\ 0000008C .... LDR.N R0,??DataTable3_4 ;; 0x40064006
\ 0000008E 0078 LDRB R0,[R0, #+0]
\ 00000090 C0F38100 UBFX R0,R0,#+2,#+2
\ 00000094 C0B2 UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
\ 00000096 0128 CMP R0,#+1
\ 00000098 F8D1 BNE.N ??mcg_pee_2_blpi_5
180
181 } // end MCG PEE to BLPI
\ 0000009A 7047 BX LR ;; return
182 /********************************************************************/
\ In section .text, align 2, keep-with-next
183 void mcg_blpi_2_pee(void)
184 {
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