📄 sysinit.s
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MOVS R2,#+0
MOVS R1,#+0
MOVS R0,#+0
BL set_sys_dividers
// 129 //设置VCO分频器，使能PLL为50MHz, LOLIE=0, PLLS=1, CME=0, VDIV=1
// 130 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(1); //VDIV = 1 (x25)
LDR.N R0,??DataTable3_15 ;; 0x40064005
MOVS R1,#+65
STRB R1,[R0, #+0]
// 131 pll_freq = 50;
MOVS R1,#+50
// 132 break;
B.N ??pll_init_9
// 133 case 1:
// 134 //设置系统分频器
// 135 //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
// 136 set_sys_dividers(0,1,1,3);
??pll_init_7:
MOVS R3,#+3
MOVS R2,#+1
MOVS R1,#+1
MOVS R0,#+0
BL set_sys_dividers
// 137 //设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
// 138 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 26 (x50)
LDR.N R0,??DataTable3_15 ;; 0x40064005
MOVS R1,#+90
STRB R1,[R0, #+0]
// 139 pll_freq = 100;
MOVS R1,#+100
// 140 break;
B.N ??pll_init_9
// 141 case 2:
// 142 //设置系统分频器
// 143 //MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4
// 144 set_sys_dividers(0,1,1,3);
??pll_init_6:
MOVS R3,#+3
MOVS R2,#+1
MOVS R1,#+1
MOVS R0,#+0
BL set_sys_dividers
// 145 //设置VCO分频器，使能PLL为96MHz, LOLIE=0, PLLS=1, CME=0, VDIV=24
// 146 MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48)
LDR.N R0,??DataTable3_15 ;; 0x40064005
MOVS R1,#+88
STRB R1,[R0, #+0]
// 147 pll_freq = 96;
MOVS R1,#+96
// 148 break;
B.N ??pll_init_9
// 149 case 3:
// 150 //设置系统分频器
// 151 //MCG=PLL, core = MCG, bus = MCG, FlexBus = MCG, Flash clock= MCG/2
// 152 set_sys_dividers(0,0,0,1);
??pll_init_8:
MOVS R3,#+1
MOVS R2,#+0
MOVS R1,#+0
MOVS R0,#+0
BL set_sys_dividers
// 153 //设置VCO分频器，使能PLL为48MHz, LOLIE=0, PLLS=1, CME=0, VDIV=0
// 154 MCG_C6 = MCG_C6_PLLS_MASK; //VDIV = 0 (x24)
LDR.N R0,??DataTable3_15 ;; 0x40064005
MOVS R1,#+64
STRB R1,[R0, #+0]
// 155 pll_freq = 48;
MOVS R1,#+48
// 156 break;
// 157 }
// 158 while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
??pll_init_9:
LDR.N R0,??DataTable3_13 ;; 0x40064006
LDRB R0,[R0, #+0]
LSLS R0,R0,#+26
BPL.N ??pll_init_9
// 159
// 160 while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
??pll_init_10:
LDR.N R0,??DataTable3_13 ;; 0x40064006
LDRB R0,[R0, #+0]
LSLS R0,R0,#+25
BPL.N ??pll_init_10
// 161
// 162 //进入PBE模式
// 163
// 164 //通过清零CLKS位来进入PEE模式
// 165 // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0
// 166 MCG_C1 &= ~MCG_C1_CLKS_MASK;
LDR.N R0,??DataTable3_12 ;; 0x40064000
LDRB R0,[R0, #+0]
ANDS R0,R0,#0x3F
LDR.N R2,??DataTable3_12 ;; 0x40064000
STRB R0,[R2, #+0]
// 167
// 168 //等待时钟状态位更新
// 169 while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};
??pll_init_11:
LDR.N R0,??DataTable3_13 ;; 0x40064006
LDRB R0,[R0, #+0]
UBFX R0,R0,#+2,#+2
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,#+3
BNE.N ??pll_init_11
// 170
// 171 //开始进入PEE模式
// 172
// 173 return pll_freq;
MOVS R0,R1
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
??pll_init_1:
POP {R1,PC} ;; return
// 174 }
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3:
DC32 0x40048038
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_1:
DC32 core_clk_mhz
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_2:
DC32 core_clk_khz
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_3:
DC32 0x40048044
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_4:
DC32 periph_clk_khz
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_5:
DC32 0x40048004
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_6:
DC32 0x40049018
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_7:
DC32 0x40048040
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_8:
DC32 0x4004b00c
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_9:
DC32 0x40064001
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_10:
DC32 0x40048034
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_11:
DC32 0x4007c008
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_12:
DC32 0x40064000
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_13:
DC32 0x40064006
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_14:
DC32 0x40064004
SECTION `.text`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
??DataTable3_15:
DC32 0x40064005
// 175
// 176 //-------------------------------------------------------------------------*
// 177 //函数名: set_sys_dividers *
// 178 //功 能: 设置系系统分频器 *
// 179 //参 数: 预分频值 *
// 180 //返 回: 无 *
// 181 //说 明: 此函数必须放在RAM里执行，否则会产生错误e2448。当FLASH时钟分频改变*
// 182 // 时，必须禁止FLASH的预取功能。在时钟分频改变之后，必须延时一小段时*
// 183 // 间才可以从新使能预取功能。 *
// 184 //-------------------------------------------------------------------------*
SECTION `.textrw`:CODE:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, SHF_WRITE | SHF_EXECINSTR
THUMB
// 185 __ramfunc void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4)
// 186 {
set_sys_dividers:
PUSH {R4-R6}
// 187 uint32 temp_reg;
// 188 uint8 i;
// 189 //保存FMC_PFAPR当前的值
// 190 temp_reg = FMC_PFAPR;
LDR.N R4,??set_sys_dividers_0 ;; 0x4001f000
LDR R4,[R4, #+0]
// 191
// 192 //通过M&PFD置位M0PFD来禁止预取功能
// 193 FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK | FMC_PFAPR_M5PFD_MASK
// 194 | FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK
// 195 | FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;
LDR.N R5,??set_sys_dividers_0 ;; 0x4001f000
LDR R5,[R5, #+0]
ORRS R5,R5,#0xFF0000
LDR.N R6,??set_sys_dividers_0 ;; 0x4001f000
STR R5,[R6, #+0]
// 196
// 197 //给时钟分频器设置期望值
// 198 SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2)
// 199 | SIM_CLKDIV1_OUTDIV3(outdiv3) | SIM_CLKDIV1_OUTDIV4(outdiv4);
LSLS R1,R1,#+24
ANDS R1,R1,#0xF000000
ORRS R0,R1,R0, LSL #+28
LSLS R1,R2,#+20
ANDS R1,R1,#0xF00000
ORRS R0,R1,R0
LSLS R1,R3,#+16
ANDS R1,R1,#0xF0000
ORRS R0,R1,R0
LDR.N R1,??set_sys_dividers_0+0x4 ;; 0x40048044
STR R0,[R1, #+0]
// 200
// 201 //等待分频器改变
// 202 for (i = 0 ; i < outdiv4 ; i++)
MOVS R0,#+0
B.N ??set_sys_dividers_1
??set_sys_dividers_2:
ADDS R0,R0,#+1
??set_sys_dividers_1:
UXTB R0,R0 ;; ZeroExt R0,R0,#+24,#+24
CMP R0,R3
BCC.N ??set_sys_dividers_2
// 203 {}
// 204
// 205 //从新存FMC_PFAPR的原始值
// 206 FMC_PFAPR = temp_reg;
LDR.N R0,??set_sys_dividers_0 ;; 0x4001f000
STR R4,[R0, #+0]
// 207
// 208 return;
POP {R4-R6}
BX LR ;; return
DATA
??set_sys_dividers_0:
DC32 0x4001f000
DC32 0x40048044
// 209 }
SECTION `.iar_vfe_header`:DATA:REORDER:NOALLOC:NOROOT(2)
SECTION_TYPE SHT_PROGBITS, 0
DATA
DC32 0
SECTION __DLIB_PERTHREAD:DATA:REORDER:NOROOT(0)
SECTION_TYPE SHT_PROGBITS, 0
SECTION __DLIB_PERTHREAD_init:DATA:REORDER:NOROOT(0)
SECTION_TYPE SHT_PROGBITS, 0
END
// 210
// 211
// 212
// 213
// 214
// 215
//
// 12 bytes in section .bss
// 426 bytes in section .text
// 76 bytes in section .textrw
//
// 502 bytes of CODE memory
// 12 bytes of DATA memory
//
//Errors: none
//Warnings: none
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