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📄 sysinit.lst

📁 Cortex-M4+example
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   \                     ??pll_init_1:
   \   000000F4   0xBD02             POP      {R1,PC}          ;; return
    174          }
    175          
    176          //-------------------------------------------------------------------------*
    177          //函数名: set_sys_dividers                                                 *
    178          //功  能: 设置系系统分频器                                                 * 
    179          //参  数: 预分频值   							   *	
    180          //返  回: 无                                                               *
    181          //说  明: 此函数必须放在RAM里执行,否则会产生错误e2448。当FLASH时钟分频改变* 
    182          //        时,必须禁止FLASH的预取功能。在时钟分频改变之后,必须延时一小段时*
    183          //	 间才可以从新使能预取功能。                                        * 
    184          //-------------------------------------------------------------------------*

   \                                 In section .textrw, align 4, keep-with-next
    185          __ramfunc void set_sys_dividers(uint32 outdiv1, uint32 outdiv2, uint32 outdiv3, uint32 outdiv4)
    186          {
   \                     set_sys_dividers:
   \   00000000   0xB470             PUSH     {R4-R6}
    187              uint32 temp_reg;
    188              uint8 i;
    189              //保存FMC_PFAPR当前的值
    190              temp_reg = FMC_PFAPR;
   \   00000002   0x4C10             LDR.N    R4,??set_sys_dividers_0  ;; 0x4001f000
   \   00000004   0x6824             LDR      R4,[R4, #+0]
    191              
    192              //通过M&PFD置位M0PFD来禁止预取功能
    193              FMC_PFAPR |= FMC_PFAPR_M7PFD_MASK | FMC_PFAPR_M6PFD_MASK | FMC_PFAPR_M5PFD_MASK
    194                               | FMC_PFAPR_M4PFD_MASK | FMC_PFAPR_M3PFD_MASK | FMC_PFAPR_M2PFD_MASK
    195                               | FMC_PFAPR_M1PFD_MASK | FMC_PFAPR_M0PFD_MASK;
   \   00000006   0x4D0F             LDR.N    R5,??set_sys_dividers_0  ;; 0x4001f000
   \   00000008   0x682D             LDR      R5,[R5, #+0]
   \   0000000A   0xF455 0x057F      ORRS     R5,R5,#0xFF0000
   \   0000000E   0x4E0D             LDR.N    R6,??set_sys_dividers_0  ;; 0x4001f000
   \   00000010   0x6035             STR      R5,[R6, #+0]
    196              
    197              //给时钟分频器设置期望值  
    198              SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) 
    199                                | SIM_CLKDIV1_OUTDIV3(outdiv3) | SIM_CLKDIV1_OUTDIV4(outdiv4);
   \   00000012   0x0609             LSLS     R1,R1,#+24
   \   00000014   0xF011 0x6170      ANDS     R1,R1,#0xF000000
   \   00000018   0xEA51 0x7000      ORRS     R0,R1,R0, LSL #+28
   \   0000001C   0x0511             LSLS     R1,R2,#+20
   \   0000001E   0xF411 0x0170      ANDS     R1,R1,#0xF00000
   \   00000022   0x4308             ORRS     R0,R1,R0
   \   00000024   0x0419             LSLS     R1,R3,#+16
   \   00000026   0xF411 0x2170      ANDS     R1,R1,#0xF0000
   \   0000002A   0x4308             ORRS     R0,R1,R0
   \   0000002C   0x4906             LDR.N    R1,??set_sys_dividers_0+0x4  ;; 0x40048044
   \   0000002E   0x6008             STR      R0,[R1, #+0]
    200              
    201              //等待分频器改变
    202              for (i = 0 ; i < outdiv4 ; i++)
   \   00000030   0x2000             MOVS     R0,#+0
   \   00000032   0xE000             B.N      ??set_sys_dividers_1
   \                     ??set_sys_dividers_2:
   \   00000034   0x1C40             ADDS     R0,R0,#+1
   \                     ??set_sys_dividers_1:
   \   00000036   0xB2C0             UXTB     R0,R0            ;; ZeroExt  R0,R0,#+24,#+24
   \   00000038   0x4298             CMP      R0,R3
   \   0000003A   0xD3FB             BCC.N    ??set_sys_dividers_2
    203              {}
    204              
    205              //从新存FMC_PFAPR的原始值
    206              FMC_PFAPR = temp_reg; 
   \   0000003C   0x4801             LDR.N    R0,??set_sys_dividers_0  ;; 0x4001f000
   \   0000003E   0x6004             STR      R4,[R0, #+0]
    207              
    208              return;
   \   00000040   0xBC70             POP      {R4-R6}
   \   00000042   0x4770             BX       LR               ;; return
   \                     ??set_sys_dividers_0:
   \   00000044   0x4001F000         DC32     0x4001f000
   \   00000048   0x40048044         DC32     0x40048044
    209          }

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3:
   \   00000000   0x40048038         DC32     0x40048038

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_1:
   \   00000000   0x........         DC32     core_clk_mhz

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_2:
   \   00000000   0x........         DC32     core_clk_khz

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_3:
   \   00000000   0x40048044         DC32     0x40048044

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_4:
   \   00000000   0x........         DC32     periph_clk_khz

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_5:
   \   00000000   0x40048004         DC32     0x40048004

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_6:
   \   00000000   0x40049018         DC32     0x40049018

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_7:
   \   00000000   0x40048040         DC32     0x40048040

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_8:
   \   00000000   0x4004B00C         DC32     0x4004b00c

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_9:
   \   00000000   0x40064001         DC32     0x40064001

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_10:
   \   00000000   0x40048034         DC32     0x40048034

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_11:
   \   00000000   0x4007C008         DC32     0x4007c008

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_12:
   \   00000000   0x40064000         DC32     0x40064000

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_13:
   \   00000000   0x40064006         DC32     0x40064006

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_14:
   \   00000000   0x40064004         DC32     0x40064004

   \                                 In section .text, align 4, keep-with-next
   \                     ??DataTable3_15:
   \   00000000   0x40064005         DC32     0x40064005
    210          
    211          
    212          
    213          
    214          
    215          

   Maximum stack usage in bytes:

   .cstack Function
   ------- --------
        0  fb_clk_init
        8  pll_init
             8 -> set_sys_dividers
       12  set_sys_dividers
        8  sysinit
             8 -> fb_clk_init
             8 -> pll_init
             8 -> trace_clk_init
        0  trace_clk_init


   Section sizes:

   Bytes  Function/Label
   -----  --------------
       4  ??DataTable3
       4  ??DataTable3_1
       4  ??DataTable3_10
       4  ??DataTable3_11
       4  ??DataTable3_12
       4  ??DataTable3_13
       4  ??DataTable3_14
       4  ??DataTable3_15
       4  ??DataTable3_2
       4  ??DataTable3_3
       4  ??DataTable3_4
       4  ??DataTable3_5
       4  ??DataTable3_6
       4  ??DataTable3_7
       4  ??DataTable3_8
       4  ??DataTable3_9
       4  core_clk_khz
       4  core_clk_mhz
      22  fb_clk_init
       4  periph_clk_khz
     246  pll_init
      76  set_sys_dividers
      72  sysinit
      22  trace_clk_init

 
  12 bytes in section .bss
 426 bytes in section .text
  76 bytes in section .textrw
 
 502 bytes of CODE memory
  12 bytes of DATA memory

Errors: none
Warnings: none

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