dac threshold set.c

TI官方提供的AMR

#include "MSP430xw42x.h"

//PSM not used during calibration, so define a "dummy" PSM
const unsigned char PSMCalib[] = {
                                   0x00,     // Init
                                   0x00,     // Init
                                   0x00,     // Init
                                   0x00,     // Init
                                 };

void SIFCalib (void)
{
  volatile unsigned int j;

  // Starting point when "looking" for sensor input values
  const unsigned int DAC_lo_start = 0x350;  
  
  unsigned int DAC0_lo;                     // Lowest val recorded for DAC0/1
  unsigned int DAC0_hi;                     // Highest val recorded for DAC0/1
  unsigned int DAC2_lo;                     // Lowest val recorded for DAC2/3
  unsigned int DAC2_hi;                     // Highest val recorded for DAC2/3

  unsigned int s1_gap=0,s2_gap=0;           // Gap between DACn_hi and DACn_lo

  // Initialize Timing State Machine
  SIFTSM0 = 0x0000;   // Reset dummy cycle.  DAC=off, CA=off, SIFEX=off
  SIFTSM1 = 0x111C;   // 3xSMCLK; DAC=CA=SIFLCEN=on; SIFCH=0.  Measure SIFCH0
  SIFTSM2 = 0x015C;   // 1xSMCLK; Turn on latch
  SIFTSM3 = 0x111D;   // 3xSMCLK; Change to SIFCH.1.  Measure SIFCH1 (latch off)
  SIFTSM4 = 0x015D;   // 1xSMCLK; Turn on latch
  SIFTSM5 = 0x0200;   // Stop.
    
  // Initialize Control Registers
  SIFCTL2 = SIFSH;          // S&H on; test, DAC/CA override, AVcc/2, exc off
  SIFCTL3 = SIFS2_1+SIFS1_0; // SIF0OUT=S1, SIF1OUT=S2; IFG3 set each CNT1 count
  SIFCTL4 = 0x0000;         // No counting; Q7/Q6 disable; TSM rate = ACLK/2
  SIFCTL5 = 0x0000;         // Periodic TSM; SIFCLK = SMCLK, MUST USE LPM0
  SIFPSMV = (unsigned int) &PSMCalib;   // Signal Processing (Offset address location) 256 bytes from FA00h
  SIFCTL1 |= 0x0001;        //   SIF_EN=1


  // *** Calibrate ***

  // Initialize with extreme highs/lows
  DAC0_lo = 0x3FF;
  DAC0_hi = 0x000;
  DAC2_lo = 0x3FF;
  DAC2_hi = 0x000;

  // For each sensor, for each of 0xFF samples, lower DAC until input 
  // is located; capture record highs/lows.  The gap between high and low must 
  // exceed a minimum value, to help ensure quality, or else exercise is 
  // repeated.  
  while((s1_gap<27) && (s2_gap<27))  //39
  {
    //********  Sensor 1 Level Detect *************************
    for(j=0;j<0xFF;j++)
    {
      SIFDACR0 = DAC_lo_start;             // Initialize DAC registers
      SIFDACR1 = DAC_lo_start;
      SIFCTL1 = SIFIE1+SIFEN;              // IE1 -- int after each TSM cycle
      _BIS_SR(LPM3_bits + GIE);            // Wait for cycle so SIFxOUT updated

      while (!(SIFCTL3 & SIF0OUT))
      {
        SIFDACR0=SIFDACR0-1;
        SIFDACR1=SIFDACR1-1;
        _BIS_SR(LPM3_bits + GIE);          // Wait for cycle so SIFxOUT updated
      }
      SIFCTL1 &= ~SIFIE1;                  // Disable interrupt
      
      // Is this a record high / record low?  
      if(SIFDACR0 < DAC0_lo)
        DAC0_lo = SIFDACR0; 
      if (SIFDACR0 > DAC0_hi)
        DAC0_hi = SIFDACR0;
      
      P6OUT = j & 0x00FF;
    }
  
    //********  Sensor 2 Level Detect *************************
    for(j=0;j<0xFF;j++)
    {
      SIFDACR2 = DAC_lo_start;             // Initialize DAC registers
      SIFDACR3 = DAC_lo_start;
      SIFCTL1 = SIFIE1+SIFEN;              // IE1 -- int after each TSM cycle
      _BIS_SR(LPM3_bits + GIE);            // Wait for cycle so SIFxOUT updated

      while (!(SIFCTL3 & SIF1OUT))
      {
        SIFDACR2=SIFDACR2-1;
        SIFDACR3=SIFDACR3-1;
        _BIS_SR(LPM3_bits + GIE);          // Wait for cycle so SIFxOUT updated
      }
      SIFCTL1 &= ~SIFIE1;                  // Disable interrupt
      
     // Is this a record high / record low?  
      if(SIFDACR2 < DAC2_lo)
        DAC2_lo = SIFDACR2;
      if (SIFDACR2 > DAC2_hi)
        DAC2_hi = SIFDACR2;
  
      P6OUT = j & 0x00FF;
    }

    s1_gap = DAC0_hi-DAC0_lo;
    s2_gap = DAC2_hi-DAC2_lo;
  }
  
  // Find the average of the high and low, add hysteresis, and configure DAC 
  // registers for operation
  SIFDACR0 = (DAC0_lo + DAC0_hi) / 2;
  SIFDACR1 = SIFDACR0;
  SIFDACR0 = SIFDACR0 + 5;
  SIFDACR1 = SIFDACR1 - 5;
  SIFDACR2 = (DAC2_lo + DAC2_hi) / 2;
  SIFDACR3 = SIFDACR2;
  SIFDACR2 = SIFDACR2 + 5;
  SIFDACR3 = SIFDACR3 - 5;

  SIFCTL1 = 0;                              // Disable SIF
}