cc2500_cfg.c

基于MDK的LPC1100处理器开发应用例程

/*CC2500 CONFIG file*/

#include "App.h"


volatile uint32_t interruptOverRunStat1 = 0;
volatile uint32_t interruptRxTimeoutStat1 = 0;


/**  SSP0_IRQHandler */
void SSP0_IRQHandler(void)
{
  uint32_t regValue;

  regValue = LPC_SSP0->MIS;
  if ( regValue & SSP_MIS_ROR )/* receive OverRun */
  {
	interruptOverRunStat1++;
	LPC_SSP0->ICR = SSP_ICR_ROR;	/* clear interrupt */
  }
  if ( regValue & SSP_MIS_RT )/* receive Timeout  */
  {
	interruptRxTimeoutStat1++;
	LPC_SSP0->ICR = SSP_ICR_RT;	/* clear interrupt */
  }
 
  return;
}



void NWK_DELAY(uint16_t milliseconds)
{
	int i,iTemp=50;//1MS = 50 * 1000 T  //31;
	while (milliseconds)
	{
		while(1)
		{
			if(iTemp == 0)
			{
				break;
			}
			for( i=0; i<1000; i++);//for( i=0; i<250; i++);
			iTemp--;
		}
		milliseconds--;
	}
}


//next code are used for test. add by mary
void RFSendPacket(uint8_t *txBuffer, uint8_t size)
{
	int i=0,j=0;
	mrfiSpiWriteTxFifo(txBuffer, size);
	//TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
    //TI_CC_SPIStrobe(TI_CCxxx0_STX);         // Change state to TX, initiating
                                            // data transfer
	//size = mrfiSpiReadReg(TXBYTES);

	mrfiSpiCmdStrobe( STX );

	while(1)
	{
		if(GPIO_ReadInputPin(CGDOPort, CGDO0))
		{
			break;
		}
		if(j>10000)
		{
			break;
		}
		if(i>=10000)
		{
			i=0;
			j++;
		}
		i++;
	}
	//while(!GPIO_ReadInputPin(CGDOPort, CGDO0));// Wait GDO0 to go hi -> sync TX'ed
	//while(GPIO_ReadInputPin(CGDOPort, CGDO0));// Wait GDO0 to clear -> end of pkt

	i=0;
	j=0;
	while(1)
	{
		if(!GPIO_ReadInputPin(CGDOPort, CGDO0))
		{
			break;
		}

		if(j>10000)
		{
			break;
		}
		if(i>=10000)
		{
			i=0;
			j++;
		}
		i++;
	}

	//size = mrfiSpiReadReg(TXBYTES);

    // to be optimized
	mrfiSpiCmdStrobe(SIDLE);
//    MRFI_DELAY(10);
//    // Flush RX FIFO
    mrfiSpiCmdStrobe(SFTX);
//    MRFI_DELAY(10);

}

void SendCurInfo(void)
{
	static int iTemp = 0;

	txBuffer[0] = 4;//2;						   // Packet length
	txBuffer[1] = 0x01; 					   // Packet address(初始化时设置的器件地址)
	//txBuffer[2] = iFameNum;
	txBuffer[2] = iTemp++; 					   // 要发送的数据


	if( iTemp > 10000  )
	{
		iTemp = 0;
	}

	// Send value over RF
	RFSendPacket(txBuffer, 5);
}

char RFReceivePacket(uint8_t *rxBuffer, uint8_t *length)
{
  uint8_t status[2];
  uint8_t pktLen;
  int i=0;

  //if (CurrentMode != STATE_RX)
  {
       mrfiSpiCmdStrobe(SRX);
	   //MRFI_DELAY(10);
  }

  if ((mrfiSpiReadReg(RXBYTES) & TI_CCxxx0_NUM_RXBYTES))
  {
    mrfiSpiReadRxFifo(&pktLen,1); // Read length byte

    if (pktLen <= *length)                  // If pktLen size <= rxBuffer
    {
		
	  mrfiSpiReadRxFifo(rxBuffer, pktLen); // Pull data
      *length = pktLen;                     // Return the actual size
      mrfiSpiReadRxFifo(status, 2);     // Read appended status bytes

      // The following 2 cmds should not be necessary. Investigation needed
      // Make sure that the radio is in IDLE state before flushing the FIFO
      // (Unless RXOFF_MODE has been changed, the radio should be in IDLE state at this point)
      mrfiSpiCmdStrobe(SIDLE);
	  //MRFI_DELAY(100);

      // Flush RX FIFO
      mrfiSpiCmdStrobe(SFRX);

      //printf("\r\n length is: %x",pktLen);
      //printf("\r\n data is: ");
      for(i=0; i<pktLen ;i++)
      {
    	  //printf(" %d", rxBuffer[i]);
      }
      //printf("\r\n status: %x, %x", status[0],status[1]);

      return (status[1]& 0x80);
    }                                       // Return CRC_OK bit
    else
    {
      *length = pktLen;                     // Return the large size
		mrfiSpiCmdStrobe(SIDLE);		
      mrfiSpiCmdStrobe(SFRX);      // Flush RXFIFO
      return 0;                             // Error
    }
  }
  else
      return 0;                             // Error
}


void writeRFSettings(void)
{
    // Write register settings
    mrfiSpiWriteReg(IOCFG2,   0x0B);  // GDO2 output pin config.
    mrfiSpiWriteReg(IOCFG0,   0x06);  // GDO0 output pin config.
    mrfiSpiWriteReg(PKTLEN,   0xFF);  // Packet length.
    //mrfiSpiWriteReg(PKTLEN,   0x2);  // Packet length.
    mrfiSpiWriteReg(PKTCTRL1, 0x05);  // Packet automation control.
    mrfiSpiWriteReg(PKTCTRL0, 0x05);  // Packet automation control.
    //mrfiSpiWriteReg(PKTCTRL0, 0x04);  // Packet automation control.
    mrfiSpiWriteReg(ADDR,     0x01);  // Device address.************
    mrfiSpiWriteReg(CHANNR,   0x00); // Channel number.
    mrfiSpiWriteReg(FSCTRL1,  0x07); // Freq synthesizer control.
    mrfiSpiWriteReg(FSCTRL0,  0x00); // Freq synthesizer control.
    mrfiSpiWriteReg(FREQ2,    0x5D); // Freq control word, high byte
    mrfiSpiWriteReg(FREQ1,    0x93); // Freq control word, mid byte.
    mrfiSpiWriteReg(FREQ0,    0xB1); // Freq control word, low byte.
    mrfiSpiWriteReg(MDMCFG4,  0x2D); // Modem configuration.
    mrfiSpiWriteReg(MDMCFG3,  0x3B); // Modem configuration.
    mrfiSpiWriteReg(MDMCFG2,  0x73); // Modem configuration.
    mrfiSpiWriteReg(MDMCFG1,  0x22); // Modem configuration.
    mrfiSpiWriteReg(MDMCFG0,  0xF8); // Modem configuration.
    mrfiSpiWriteReg(DEVIATN,  0x00); // Modem dev (when FSK mod en)
    mrfiSpiWriteReg(MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    mrfiSpiWriteReg(MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    mrfiSpiWriteReg(FOCCFG,   0x1D); // Freq Offset Compens. Config
    mrfiSpiWriteReg(BSCFG,    0x1C); //  Bit synchronization config.
    mrfiSpiWriteReg(AGCCTRL2, 0xC7); // AGC control.
    mrfiSpiWriteReg(AGCCTRL1, 0x00); // AGC control.
    mrfiSpiWriteReg(AGCCTRL0, 0xB2); // AGC control.
    mrfiSpiWriteReg(FREND1,   0xB6); // Front end RX configuration.
    mrfiSpiWriteReg(FREND0,   0x10); // Front end RX configuration.
    mrfiSpiWriteReg(FSCAL3,   0xEA); // Frequency synthesizer cal.
    mrfiSpiWriteReg(FSCAL2,   0x0A); // Frequency synthesizer cal.
    mrfiSpiWriteReg(FSCAL1,   0x00); // Frequency synthesizer cal.
    mrfiSpiWriteReg(FSCAL0,   0x11); // Frequency synthesizer cal.
    mrfiSpiWriteReg(FSTEST,   0x59); // Frequency synthesizer cal.
    mrfiSpiWriteReg(TEST2,    0x88); // Various test settings.
    mrfiSpiWriteReg(TEST1,    0x31); // Various test settings.
    mrfiSpiWriteReg(TEST0,    0x0B);  // Various test settings.
}