📄 lpc11xx.h
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typedef struct
{
union {
__IO uint32_t MASKED_ACCESS[4096];
struct {
uint32_t RESERVED0[4095];
__IO uint32_t DATA;
};
};
uint32_t RESERVED1[4096];
__IO uint32_t DIR;
__IO uint32_t IS;
__IO uint32_t IBE;
__IO uint32_t IEV;
__IO uint32_t IE;
__IO uint32_t RIS;
__IO uint32_t MIS;
__IO uint32_t IC;
} GPIO_TypeDef;
/*------------- Timer (TMR) --------------------------------------------------*/
typedef struct
{
__IO uint32_t IR;
__IO uint32_t TCR;
__IO uint32_t TC;
__IO uint32_t PR;
__IO uint32_t PC;
__IO uint32_t MCR;
__IO uint32_t MR0;
__IO uint32_t MR1;
__IO uint32_t MR2;
__IO uint32_t MR3;
__IO uint32_t CCR;
__I uint32_t CR0;
uint32_t RESERVED1[3];
__IO uint32_t EMR;
uint32_t RESERVED2[12];
__IO uint32_t CTCR;
__IO uint32_t PWMC;
} TMR_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
union {
__I uint32_t RBR;
__O uint32_t THR;
__IO uint32_t DLL;
};
union {
__IO uint32_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint32_t FCR;
};
__IO uint32_t LCR;
__IO uint32_t MCR;
__I uint32_t LSR;
__I uint32_t MSR;
__IO uint32_t SCR;
__IO uint32_t ACR;
__IO uint32_t ICR;
__IO uint32_t FDR;
uint32_t RESERVED0;
__IO uint32_t TER;
uint32_t RESERVED1[6];
__IO uint32_t RS485CTRL;
__IO uint32_t ADRMATCH;
__IO uint32_t RS485DLY;
__I uint32_t FIFOLVL;
} UART_TypeDef;
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
typedef struct
{
__IO uint32_t CR0;
__IO uint32_t CR1;
__IO uint32_t DR;
__I uint32_t SR;
__IO uint32_t CPSR;
__IO uint32_t IMSC;
__IO uint32_t RIS;
__IO uint32_t MIS;
__IO uint32_t ICR;
} SSP_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
typedef struct
{
__IO uint32_t CONSET;
__I uint32_t STAT;
__IO uint32_t DAT;
__IO uint32_t ADR0;
__IO uint32_t SCLH;
__IO uint32_t SCLL;
__O uint32_t CONCLR;
__IO uint32_t MMCTRL;
__IO uint32_t ADR1;
__IO uint32_t ADR2;
__IO uint32_t ADR3;
__I uint32_t DATA_BUFFER;
__IO uint32_t MASK0;
__IO uint32_t MASK1;
__IO uint32_t MASK2;
__IO uint32_t MASK3;
} I2C_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
{
__IO uint32_t MOD;
__IO uint32_t TC;
__O uint32_t FEED;
__I uint32_t TV;
} WDT_TypeDef;
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t GDR;
uint32_t RESERVED0;
__IO uint32_t INTEN;
__I uint32_t DR0;
__I uint32_t DR1;
__I uint32_t DR2;
__I uint32_t DR3;
__I uint32_t DR4;
__I uint32_t DR5;
__I uint32_t DR6;
__I uint32_t DR7;
__I uint32_t STAT;
} ADC_TypeDef;
/*------------- CAN Controller (CAN) ----------------------------*/
typedef struct
{
__IO uint32_t CNTL; /* 0x000 */
__IO uint32_t STAT;
__IO uint32_t EC;
__IO uint32_t BT;
__IO uint32_t INT;
__IO uint32_t TEST;
__IO uint32_t BRPE;
uint32_t RESERVED0;
__IO uint32_t IF1_CMDREQ; /* 0x020 */
__IO uint32_t IF1_CMDMSK;
__IO uint32_t IF1_MSK1;
__IO uint32_t IF1_MSK2;
__IO uint32_t IF1_ARB1;
__IO uint32_t IF1_ARB2;
__IO uint32_t IF1_MCTRL;
__IO uint32_t IF1_DA1;
__IO uint32_t IF1_DA2;
__IO uint32_t IF1_DB1;
__IO uint32_t IF1_DB2;
uint32_t RESERVED1[13];
__IO uint32_t IF2_CMDREQ; /* 0x080 */
__IO uint32_t IF2_CMDMSK;
__IO uint32_t IF2_MSK1;
__IO uint32_t IF2_MSK2;
__IO uint32_t IF2_ARB1;
__IO uint32_t IF2_ARB2;
__IO uint32_t IF2_MCTRL;
__IO uint32_t IF2_DA1;
__IO uint32_t IF2_DA2;
__IO uint32_t IF2_DB1;
__IO uint32_t IF2_DB2;
uint32_t RESERVED2[21];
__I uint32_t TXREQ1; /* 0x100 */
__I uint32_t TXREQ2;
uint32_t RESERVED3[6];
__I uint32_t ND1; /* 0x120 */
__I uint32_t ND2;
uint32_t RESERVED4[6];
__I uint32_t IR1; /* 0x140 */
__I uint32_t IR2;
uint32_t RESERVED5[6];
__I uint32_t MSGV1; /* 0x160 */
__I uint32_t MSGV2;
uint32_t RESERVED6[6];
__IO uint32_t CLKDIV; /* 0x180 */
} CAN_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
typedef struct
{
__I uint32_t DevIntSt; /* USB Device Interrupt Registers */
__IO uint32_t DevIntEn;
__O uint32_t DevIntClr;
__O uint32_t DevIntSet;
__O uint32_t CmdCode; /* USB Device SIE Command Registers */
__I uint32_t CmdData;
__I uint32_t RxData; /* USB Device Transfer Registers */
__O uint32_t TxData;
__I uint32_t RxPLen;
__O uint32_t TxPLen;
__IO uint32_t Ctrl;
__O uint32_t DevFIQSel;
} USB_TypeDef;
#pragma no_anon_unions
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
#define FLASH_BASE (0x00000000UL)
#define RAM_BASE (0x10000000UL)
#define APB0_BASE (0x40000000UL)
#define AHB_BASE (0x50000000UL)
/* APB0 peripherals */
#define I2C_BASE (APB0_BASE + 0x00000)
#define WDT_BASE (APB0_BASE + 0x04000)
#define UART_BASE (APB0_BASE + 0x08000)
#define CT16B0_BASE (APB0_BASE + 0x0C000)
#define CT16B1_BASE (APB0_BASE + 0x10000)
#define CT32B0_BASE (APB0_BASE + 0x14000)
#define CT32B1_BASE (APB0_BASE + 0x18000)
#define ADC_BASE (APB0_BASE + 0x1C000)
#define USB_BASE (APB0_BASE + 0x20000)
#define PMU_BASE (APB0_BASE + 0x38000)
#define SSP0_BASE (APB0_BASE + 0x40000)
#define IOCON_BASE (APB0_BASE + 0x44000)
#define SYSCON_BASE (APB0_BASE + 0x48000)
#define CAN_BASE (APB0_BASE + 0x50000)
#define SSP1_BASE (APB0_BASE + 0x58000)
/* AHB peripherals */
#define GPIO_BASE (AHB_BASE + 0x00000)
#define GPIO0_BASE (AHB_BASE + 0x00000)
#define GPIO1_BASE (AHB_BASE + 0x10000)
#define GPIO2_BASE (AHB_BASE + 0x20000)
#define GPIO3_BASE (AHB_BASE + 0x30000)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define LPC_I2C (( I2C_TypeDef *) I2C_BASE)
#define LPC_WDT (( WDT_TypeDef *) WDT_BASE)
#define LPC_UART (( UART_TypeDef *) UART_BASE)
#define LPC_TMR16B0 (( TMR_TypeDef *) CT16B0_BASE)
#define LPC_TMR16B1 (( TMR_TypeDef *) CT16B1_BASE)
#define LPC_TMR32B0 (( TMR_TypeDef *) CT32B0_BASE)
#define LPC_TMR32B1 (( TMR_TypeDef *) CT32B1_BASE)
#define LPC_ADC (( ADC_TypeDef *) ADC_BASE)
#define LPC_PMU (( PMU_TypeDef *) PMU_BASE)
#define LPC_SSP0 (( SSP_TypeDef *) SSP0_BASE)
#define LPC_SSP1 (( SSP_TypeDef *) SSP1_BASE)
#define LPC_CAN (( CAN_TypeDef *) CAN_BASE)
#define LPC_IOCON (( IOCON_TypeDef *) IOCON_BASE)
#define LPC_SYSCON (( SYSCON_TypeDef *) SYSCON_BASE)
#define LPC_USB (( USB_TypeDef *) USB_BASE)
#define LPC_GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
#define LPC_GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
#define LPC_GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
#define LPC_GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
#endif // __LPC11xx_H__
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