📄 mypcioin.lst
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293
294 #define VX_C3 0xC3 // turn OFF debug LEDs...
295
296
297 // Core uses bRequest value 0xA0 for Anchor downloads/uploads...
298 // Cypress Semiconductor reserves bRequest values 0xA1 through 0xAF...
299 // Your implementation should not use the above bRequest values...
300 // Also, previous fw.c versions trap all bRequest values 0x00 through 0x0F...
301 //
302 // bRequest value: SETUPDAT[1]
C51 COMPILER V7.50 MYPCIOIN 07/03/2006 21:21:35 PAGE 6
303 // standard, 0x00 through 0x0F
304 //
305 // bmRequest value: SETUPDAT[0]
306 // standard, 0x80 IN Token
307 // vendor, 0xC0 IN Token
308 // class, 0xA0 IN Token
309 // standard, 0x00 OUT Token
310 // vendor, 0x40 OUT Token
311 // class, 0x60 OUT Token
312
313 BOOL DR_VendorCmnd( void )
314 {
315 1
316 1 // Registers which require a synchronization delay, see section 15.14
317 1 // FIFORESET FIFOPINPOLAR
318 1 // INPKTEND OUTPKTEND
319 1 // EPxBCH:L REVCTL
320 1 // GPIFTCB3 GPIFTCB2
321 1 // GPIFTCB1 GPIFTCB0
322 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
323 1 // EPxFIFOCFG EPxGPIFFLGSEL
324 1 // PINFLAGSxx EPxFIFOIRQ
325 1 // EPxFIFOIE GPIFIRQ
326 1 // GPIFIE GPIFADRH:L
327 1 // UDMACRCH:L EPxGPIFTRIG
328 1 // GPIFTRIG
329 1
330 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
331 1 // ...these have been replaced by GPIFTC[B3:B0] registers
332 1
333 1
334 1
335 1
336 1 switch( SETUPDAT[ 1 ] )
337 1 {
338 2 case VX_B2:
339 2 { // turn OFF debug LEDs...
340 3
341 3 ledX_rdvar = LED0_ON; // visual
342 3 ledX_rdvar = LED1_ON; // visual
343 3 ledX_rdvar = LED2_ON; // visual
344 3 ledX_rdvar = LED3_ON; // visual
345 3
346 3 *EP0BUF = VX_B2;
347 3
348 3 EP0BCH = 0;
349 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
350 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
351 3
352 3
353 3 break;
354 3 }
355 2 case VX_B3:
356 2 { // turn OFF debug LEDs...
357 3
358 3 ledX_rdvar = LED0_OFF; // visual
359 3 ledX_rdvar = LED1_OFF; // visual
360 3 ledX_rdvar = LED2_OFF; // visual
361 3 ledX_rdvar = LED3_OFF; // visual
362 3
363 3 *EP0BUF = VX_B3;
364 3 EP0BCH = 0;
C51 COMPILER V7.50 MYPCIOIN 07/03/2006 21:21:35 PAGE 7
365 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
366 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
367 3
368 3
369 3
370 3
371 3 break;
372 3 }
373 2
374 2 case VX_BC:
375 2 { // turn OFF debug LEDs...
376 3
377 3
378 3
379 3
380 3
381 3
382 3 *EP0BUF = num;
383 3 EP0BCH = 0;
384 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
385 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
386 3
387 3 break;
388 3 }
389 2
390 2
391 2
392 2 default:
393 2 {
394 3 ledX_rdvar = LED3_ON; // debug visual, stuck "ON" to warn developer...
395 3 return( FALSE ); // no error; command handled OK
396 3 }
397 2 }
398 1
399 1
400 1 return( FALSE ); // no error; command handled OK
401 1 }
402
403 //-----------------------------------------------------------------------------
404 // USB Interrupt Handlers
405 // The following functions are called by the USB interrupt jump table.
406 //-----------------------------------------------------------------------------
407
408 // Setup Data Available Interrupt Handler
409 void ISR_Sudav( void ) interrupt 0
410 {
411 1 GotSUD = TRUE; // Set flag
412 1 EZUSB_IRQ_CLEAR( );
413 1 USBIRQ = bmSUDAV; // Clear SUDAV IRQ
414 1 }
415
416 // Setup Token Interrupt Handler
417 void ISR_Sutok( void ) interrupt 0
418 {
419 1 EZUSB_IRQ_CLEAR( );
420 1 USBIRQ = bmSUTOK; // Clear SUTOK IRQ
421 1 }
422
423 void ISR_Sof( void ) interrupt 0
424 {
425 1 EZUSB_IRQ_CLEAR( );
426 1 USBIRQ = bmSOF; // Clear SOF IRQ
C51 COMPILER V7.50 MYPCIOIN 07/03/2006 21:21:35 PAGE 8
427 1 }
428
429 void ISR_Ures( void ) interrupt 0
430 {
431 1 if ( EZUSB_HIGHSPEED( ) )
432 1 {
433 2 pConfigDscr = pHighSpeedConfigDscr;
434 2 pOtherConfigDscr = pFullSpeedConfigDscr;
435 2 }
436 1 else
437 1 {
438 2 pConfigDscr = pFullSpeedConfigDscr;
439 2 pOtherConfigDscr = pHighSpeedConfigDscr;
440 2 }
441 1
442 1 EZUSB_IRQ_CLEAR( );
443 1 USBIRQ = bmURES; // Clear URES IRQ
444 1 }
445
446 void ISR_Susp( void ) interrupt 0
447 {
448 1 Sleep = TRUE;
449 1 EZUSB_IRQ_CLEAR( );
450 1 USBIRQ = bmSUSP;
451 1 }
452
453 void ISR_Highspeed( void ) interrupt 0
454 {
455 1 if ( EZUSB_HIGHSPEED( ) )
456 1 {
457 2 pConfigDscr = pHighSpeedConfigDscr;
458 2 pOtherConfigDscr = pFullSpeedConfigDscr;
459 2 }
460 1 else
461 1 {
462 2 pConfigDscr = pFullSpeedConfigDscr;
463 2 pOtherConfigDscr = pHighSpeedConfigDscr;
464 2 }
465 1
466 1 EZUSB_IRQ_CLEAR( );
467 1 USBIRQ = bmHSGRANT;
468 1 }
469 void ISR_Ep0ack( void ) interrupt 0
470 {
471 1 }
472 void ISR_Stub( void ) interrupt 0
473 {
474 1 }
475 void ISR_Ep0in( void ) interrupt 0
476 {
477 1 }
478 void ISR_Ep0out( void ) interrupt 0
479 {
480 1 }
481 void ISR_Ep1in( void ) interrupt 0
482 {
483 1 }
484 void ISR_Ep1out( void ) interrupt 0
485 {
486 1 }
487 void ISR_Ep2inout( void ) interrupt 0
488 {
C51 COMPILER V7.50 MYPCIOIN 07/03/2006 21:21:35 PAGE 9
489 1 }
490 void ISR_Ep4inout( void ) interrupt 0
491 {
492 1 }
493 void ISR_Ep6inout( void ) interrupt 0
494 {
495 1 }
496 void ISR_Ep8inout( void ) interrupt 0
497 {
498 1 }
499 void ISR_Ibn( void ) interrupt 0
500 {
501 1 }
502 void ISR_Ep0pingnak( void ) interrupt 0
503 {
504 1 }
505 void ISR_Ep1pingnak( void ) interrupt 0
506 {
507 1 }
508 void ISR_Ep2pingnak( void ) interrupt 0
509 {
510 1 }
511 void ISR_Ep4pingnak( void ) interrupt 0
512 {
513 1 }
514 void ISR_Ep6pingnak( void ) interrupt 0
515 {
516 1 }
517 void ISR_Ep8pingnak( void ) interrupt 0
518 {
519 1 }
520 void ISR_Errorlimit( void ) interrupt 0
521 {
522 1 }
523 void ISR_Ep2piderror( void ) interrupt 0
524 {
525 1 }
526 void ISR_Ep4piderror( void ) interrupt 0
527 {
528 1 }
529 void ISR_Ep6piderror( void ) interrupt 0
530 {
531 1 }
532 void ISR_Ep8piderror( void ) interrupt 0
533 {
534 1 }
535 void ISR_Ep2pflag( void ) interrupt 0
536 {
537 1 }
538 void ISR_Ep4pflag( void ) interrupt 0
539 {
540 1 }
541 void ISR_Ep6pflag( void ) interrupt 0
542 {
543 1 }
544 void ISR_Ep8pflag( void ) interrupt 0
545 {
546 1 }
547 void ISR_Ep2eflag( void ) interrupt 0
548 {
549 1 }
550 void ISR_Ep4eflag( void ) interrupt 0
C51 COMPILER V7.50 MYPCIOIN 07/03/2006 21:21:35 PAGE 10
551 {
552 1 }
553 void ISR_Ep6eflag( void ) interrupt 0
554 {
555 1 }
556 void ISR_Ep8eflag( void ) interrupt 0
557 {
558 1 }
559 void ISR_Ep2fflag( void ) interrupt 0
560 {
561 1 }
562 void ISR_Ep4fflag( void ) interrupt 0
563 {
564 1 }
565 void ISR_Ep6fflag( void ) interrupt 0
566 {
567 1 }
568 void ISR_Ep8fflag( void ) interrupt 0
569 {
570 1 }
571 void ISR_GpifComplete( void ) interrupt 0
572 {
573 1 }
574 void ISR_GpifWaveform( void ) interrupt 0
575 {
576 1 }
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 732 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 16 1
PDATA SIZE = ---- ----
DATA SIZE = 5 1
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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