ls154oc.v

来自「就是个译码器」· Verilog 代码 · 共 51 行

module LS154OC (indata,outdata,enable1,enable2);
input  [3:0]indata;
input  enable1,enable2;
output [15:0]outdata;
reg [15:0]temp;
wire [15:0]temp2;

always @(indata)
begin
  case(indata)
  4'h0: temp<= 16'h0001;
  4'h1: temp<= 16'h0002;
  4'h2: temp<= 16'h0004;
  4'h3: temp<= 16'h0008;
  4'h4: temp<= 16'h0010;
  4'h5: temp<= 16'h0020;
  4'h6: temp<= 16'h0040;
  4'h7: temp<= 16'h0080;
  4'h8: temp<= 16'h0100;
  4'h9: temp<= 16'h0200;
  4'hA: temp<= 16'h0400;
  4'hB: temp<= 16'h0800;
  4'hC: temp<= 16'h1000;
  4'hD: temp<= 16'h2000;
  4'hE: temp<= 16'h4000;
  4'hF: temp<= 16'h8000;
  default:  temp<=16'h0000;
  endcase
end

assign temp2 = (!(!enable1&!enable2))?16'h0:temp;
opndrn ouy0(!temp2[0],outdata[0]);
opndrn ouy1(!temp2[1],outdata[1]);
opndrn ouy2(!temp2[2],outdata[2]);
opndrn ouy3(!temp2[3],outdata[3]);
opndrn ouy4(!temp2[4],outdata[4]);
opndrn ouy5(!temp2[5],outdata[5]);
opndrn ouy6(!temp2[6],outdata[6]);
opndrn ouy7(!temp2[7],outdata[7]);
opndrn ouy8(!temp2[8],outdata[8]);
opndrn ouy9(!temp2[9],outdata[9]);
opndrn ouy10(!temp2[10],outdata[10]);
opndrn ouy11(!temp2[11],outdata[11]);
opndrn ouy12(!temp2[12],outdata[12]);
opndrn ouy13(!temp2[13],outdata[13]);
opndrn ouy14(!temp2[14],outdata[14]);
opndrn ouy15(!temp2[15],outdata[15]);

endmodule