at91rm9200.h

atmel9200 vxworks bsp

#define UART_CR_DTR_ENA			(1<<16)
#define UART_CR_DTR_DIS			(1<<17)
#define UART_CR_RTS_ENA			(1<<18)
#define UART_CR_RTS_DIS			(1<<19)

/*
 *	for US_MR:
 */

#define UART_MR_UART_MODE_NORMAL		0
#define UART_MR_UART_MODE_RS485			1
#define UART_MR_UART_MODE_HWHANDS		2
#define UART_MR_UART_MODE_MODEM			3
#define UART_MR_UART_MODE_ISO07816_0	4
#define UART_MR_UART_MODE_ISO07816_1	6
#define UART_MR_UART_MODE_IRDA			8
#define UART_MR_CLK_USE_MCK				(0<<4)
#define UART_MR_CLK_USE_MCKDIV			(1<<4)
#define UART_MR_CLK_USE_SCK				(3<<4)
#define UART_MR_CHAR_5BIT				(0<<6)
#define UART_MR_CHAR_6BIT				(1<<6)
#define UART_MR_CHAR_7BIT				(2<<6)
#define UART_MR_CHAR_8BIT				(3<<6)
#define UART_MR_SYNC_MODE				(1<<8)
#define UART_MR_PARITY_EVEN				(0<<9)
#define UART_MR_PARITY_ODD				(1<<9)
#define UART_MR_PARITY_FORCE_0			(2<<9)
#define UART_MR_PARITY_FORCE_1			(3<<9)
#define UART_MR_PARITY_NONE				(4<<9)
#define UART_MR_MULTI_DROP				(6<<9)
#define UART_MR_STOP_1BIT				(0<<12)
#define UART_MR_STOP_1BIT5				(1<<12)
#define UART_MR_STOP_2BIT				(2<<12)
#define UART_MR_TEST_NORMAL_MODE		(0<<14)
#define UART_MR_TEST_EACO_MODE			(1<<14)
#define UART_MR_TEST_LOCALLOOP_NORMAL	(2<<14)
#define UART_MR_TEST_REMOTELOOP_NORMAL	(3<<14)
#define UART_MR_MOSTBIT_FIRST			(1<<16)
#define UART_MR_CHAR_9BIT				(1<<17)
#define UART_MR_CLK_OUT_ENA				(1<<18)
#define UART_MR_8X_OVER_SAMP			(1<<19)
#define UART_MR_INHB_NACK				(1<<20)
#define UART_MR_DISABLE_NACK			(1<<21)
#define UART_MR_MAX_INTERATION			(0<<22)
#define UART_MR_IRDA_FILTER_ON			(1<<28)

#define UART_IE_DR_RXRDY		(1<<0)		/*RXRDY Interrupt Enable                                  */
#define UART_IE_DR_TXRDY        (1<<1)		/*TXRDY Interrupt Enable                                  */
#define UART_IE_DR_RXBRK        (1<<2)		/*RXBRK: Receiver Break Interrupt Enable                  */
#define UART_IE_DR_ENDRX        (1<<3)		/*ENDRX: End of Receive Transfer Interrupt Enable         */
#define UART_IE_DR_ENDTX        (1<<4)		/*ENDTX: End of Transmit Interrupt Enable                 */
#define UART_IE_DR_OVRE         (1<<5)		/*OVRE: Overrun Error Interrupt Enable                    */
#define UART_IE_DR_FRAME        (1<<6)		/*FRAME: Framing Error Interrupt Enable                   */
#define UART_IE_DR_PARE         (1<<7)		/*PARE: Parity Error Interrupt Enable                     */
#define UART_IE_DR_TIMEOUT      (1<<8)		/*TIMEOUT: Time-out Interrupt Enable                      */
#define UART_IE_DR_TXEMPTY      (1<<9)		/*TXEMPTY: TXEMPTY Interrupt Enable                       */
#define UART_IE_DR_ITERATION    (1<<10)		/*ITERATION: Iteration Interrupt Enable                   */
#define UART_IE_DR_TXBUFE       (1<<11)		/*TXBUFE: Buffer Empty Interrupt Enable                   */
#define UART_IE_DR_RXBUFF       (1<<12)		/*RXBUFF: Buffer Full Interrupt Enable                    */
#define UART_IE_DR_NACK         (1<<13)		/*NACK: Non Acknowledge Interrupt Enable                  */
#define UART_IE_DR_RIIC         (1<<16)		/*RIIC: Ring Indicator Input Change Enable                */
#define UART_IE_DR_DSRIC        (1<<17)		/*DSRIC: Data Set Ready Input Change Enable               */
#define UART_IE_DR_DCDIC        (1<<18)		/*DCDIC: Data Carrier Detect Input Change Interrupt Enable*/
#define UART_IE_DR_CTSIC        (1<<19)		/*CTSIC: Clear to Send Input Change Interrupt Enable      */
 
/* UART_CSR :status register bit layout */ 
#define UART_CSR_RXRDY		  (1<<0)	
#define UART_CSR_TXRDY        (1<<1)	
#define UART_CSR_RXBRK        (1<<2)	
#define UART_CSR_ENDRX        (1<<3)	
#define UART_CSR_ENDTX        (1<<4)	
#define UART_CSR_OVRE         (1<<5)	
#define UART_CSR_FRAME        (1<<6)	
#define UART_CSR_PARE         (1<<7)	
#define UART_CSR_TIMEOUT      (1<<8)	
#define UART_CSR_TXEMPTY      (1<<9)	
#define UART_CSR_ITERATION    (1<<10)	
#define UART_CSR_TXBUFE       (1<<11)	
#define UART_CSR_RXBUFF       (1<<12)	
#define UART_CSR_NACK         (1<<13)	
#define UART_CSR_RIIC         (1<<16)	
#define UART_CSR_DSRIC        (1<<17)	
#define UART_CSR_DCDIC        (1<<18)	
#define UART_CSR_CTSIC        (1<<19)	

#define UART_CSR_RI           (1<<20)	
#define UART_CSR_DSR          (1<<21)	
#define UART_CSR_DCD          (1<<22)	
#define UART_CSR_CTS          (1<<23)	

#define UART_TANS_TIME_GUARD	1

#define UDP_BASE_ADDR	0xFFFB0000

#ifndef _ASMLANGUAGE

typedef struct _UDP_S {
	AT91_REG	 UDP_NUM; 		/* Frame Number Register				*/
	AT91_REG	 UDP_GLBSTATE; 	/* Global State Register                */
	AT91_REG	 UDP_FADDR; 	/* Function Address Register            */
	AT91_REG	 Reserved0[1]; 	/*                                      */
	AT91_REG	 UDP_IER; 		/* Interrupt Enable Register            */
	AT91_REG	 UDP_IDR; 		/* Interrupt Disable Register           */
	AT91_REG	 UDP_IMR; 		/* Interrupt Mask Register              */
	AT91_REG	 UDP_ISR; 		/* Interrupt Status Register            */
	AT91_REG	 UDP_ICR; 		/* Interrupt Clear Register             */
	AT91_REG	 Reserved1[1]; 	/*                                      */
	AT91_REG	 UDP_RSTEP; 	/* Reset Endpoint Register              */
	AT91_REG	 Reserved2[1]; 	/*                                      */
	AT91_REG	 UDP_CSR[8]; 	/* Endpoint Control and Status Register	*/
	AT91_REG	 UDP_FDR[8]; 	/* Endpoint FIFO Data Register          */
}UDP_S;

#endif

#define MCI_BASE_ADDR	0xFFFB4000

#ifndef _ASMLANGUAGE

typedef struct _MCI_S
{
	AT91_REG	 MCI_CR; 		/* MCI Control Register				*/
	AT91_REG	 MCI_MR; 		/* MCI Mode Register                */
	AT91_REG	 MCI_DTOR; 		/* MCI Data Timeout Register        */
	AT91_REG	 MCI_SDCR; 		/* MCI SD Card Register             */
	AT91_REG	 MCI_ARGR; 		/* MCI Argument Register            */
	AT91_REG	 MCI_CMDR; 		/* MCI Command Register             */
	AT91_REG	 Reserved0[2]; 	/*                                  */
	AT91_REG	 MCI_RSPR[4]; 	/* MCI Response Register            */
	AT91_REG	 MCI_RDR; 		/* MCI Receive Data Register        */
	AT91_REG	 MCI_TDR; 		/* MCI Transmit Data Register       */
	AT91_REG	 Reserved1[2]; 	/*                                  */
	AT91_REG	 MCI_SR; 		/* MCI Status Register              */
	AT91_REG	 MCI_IER; 		/* MCI Interrupt Enable Register    */
	AT91_REG	 MCI_IDR; 		/* MCI Interrupt Disable Register   */
	AT91_REG	 MCI_IMR; 		/* MCI Interrupt Mask Register      */
	AT91_REG	 Reserved2[44]; 
	PDC_S		 MCI_PDC;
}MCI_S;

#endif

#define EMAC_BASE_ADDR	0xFFFBC000

#ifndef _ASMLANGUAGE

typedef struct _ETH_STAT_S
{
	AT91_REG	 EMAC_FRA; 		/* Frames Transmitted OK Register           */ 
	AT91_REG	 EMAC_SCOL; 	/* Single Collision Frame Register          */
	AT91_REG	 EMAC_MCOL; 	/* Multiple Collision Frame Register        */
	AT91_REG	 EMAC_OK; 		/* Frames Received OK Register              */ 
	AT91_REG	 EMAC_SEQE; 	/* Frame Check Sequence Error Register      */
	AT91_REG	 EMAC_ALE; 		/* Alignment Error Register                 */ 
	AT91_REG	 EMAC_DTE; 		/* Deferred Transmission Frame Register     */ 
	AT91_REG	 EMAC_LCOL; 	/* Late Collision Register                  */
	AT91_REG	 EMAC_ECOL; 	/* Excessive Collision Register             */
	AT91_REG	 EMAC_CSE; 		/* Carrier Sense Error Register             */ 
	AT91_REG	 EMAC_TUE; 		/* Transmit Underrun Error Register         */ 
	AT91_REG	 EMAC_CDE; 		/* Code Error Register                      */ 
	AT91_REG	 EMAC_ELR; 		/* Excessive Length Error Register          */ 
	AT91_REG	 EMAC_RJB; 		/* Receive Jabber Register                  */ 
	AT91_REG	 EMAC_USF; 		/* Undersize Frame Register                 */ 
	AT91_REG	 EMAC_SQEE; 	/* SQE Test Error Register                  */
	AT91_REG	 EMAC_DRFC; 	/* Discarded RX Frame Register              */
}ETH_STAT_S;	


typedef struct _EMAC_S {                                             
	AT91_REG	 EMAC_CTL; 		/* Network Control Register            		*/      
	AT91_REG	 EMAC_CFG; 		/* Network Configuration Register           */ 
	AT91_REG	 EMAC_SR; 		/* Network Status Register                  */ 
	AT91_REG	 EMAC_TAR; 		/* Transmit Address Register                */ 
	AT91_REG	 EMAC_TCR; 		/* Transmit Control Register                */ 
	AT91_REG	 EMAC_TSR; 		/* Transmit Status Register                 */ 
	AT91_REG	 EMAC_RBQP; 	/* Receive Buffer Queue Pointer             */
	AT91_REG	 Reserved0[1]; 	/*                                          */
	AT91_REG	 EMAC_RSR; 		/* Receive Status Register                  */ 
	AT91_REG	 EMAC_ISR; 		/* Interrupt Status Register                */ 
	AT91_REG	 EMAC_IER; 		/* Interrupt Enable Register                */ 
	AT91_REG	 EMAC_IDR; 		/* Interrupt Disable Register               */ 
	AT91_REG	 EMAC_IMR; 		/* Interrupt Mask Register                  */ 
	AT91_REG	 EMAC_MAN; 		/* PHY Maintenance Register                 */ 
	AT91_REG	 Reserved1[2]; 	/*                                          */
	ETH_STAT_S	 ESTAT;
	AT91_REG	 Reserved2[3]; 	/*                                          */
	AT91_REG	 EMAC_HSH; 		/* Hash Address High[63:32]                 */ 
	AT91_REG	 EMAC_HSL; 		/* Hash Address Low[31:0]                   */ 
	AT91_REG	 EMAC_SA1L; 	/* Specific Address 1 Low, First 4 bytes    */
	AT91_REG	 EMAC_SA1H; 	/* Specific Address 1 High, Last 2 bytes    */
	AT91_REG	 EMAC_SA2L; 	/* Specific Address 2 Low, First 4 bytes    */
	AT91_REG	 EMAC_SA2H; 	/* Specific Address 2 High, Last 2 bytes    */
	AT91_REG	 EMAC_SA3L; 	/* Specific Address 3 Low, First 4 bytes    */
	AT91_REG	 EMAC_SA3H; 	/* Specific Address 3 High, Last 2 bytes    */
	AT91_REG	 EMAC_SA4L; 	/* Specific Address 4 Low, First 4 bytes    */
	AT91_REG	 EMAC_SA4H; 	/* Specific Address 4 High, Last 2 bytesr   */
} EMAC_S;



#endif 
 
#define EMAC_CTL_LB         ((unsigned int) 0x1 <<  0) 					/* (EMAC) Loopback. Optional. When set, loopback signal is at high level.*/ 
#define EMAC_CTL_LBL        ((unsigned int) 0x1 <<  1) 					/* (EMAC) Loopback local.                                                */
#define EMAC_CTL_RE         ((unsigned int) 0x1 <<  2) 					/* (EMAC) Receive enable.                                                */
#define EMAC_CTL_TE         ((unsigned int) 0x1 <<  3) 					/* (EMAC) Transmit enable.                                               */
#define EMAC_CTL_MPE        ((unsigned int) 0x1 <<  4) 					/* (EMAC) Management port enable.                                        */
#define EMAC_CTL_CSR        ((unsigned int) 0x1 <<  5) 					/* (EMAC) Clear statistics registers.                                    */
#define EMAC_CTL_ISR        ((unsigned int) 0x1 <<  6) 					/* (EMAC) Increment statistics registers.                                */
#define EMAC_CTL_WES        ((unsigned int) 0x1 <<  7) 					/* (EMAC) Write enable for statistics registers.                         */
#define EMAC_CTL_BP         ((unsigned int) 0x1 <<  8) 					/* (EMAC) Back pressure.                                                 */
/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------  */
#define EMAC_CFG_SPD        ((unsigned int) 0x1 <<  0) 					/* (EMAC) Speed.  							*/
#define EMAC_CFG_FD         ((unsigned int) 0x1 <<  1) 					/* (EMAC) Full duplex.                      */
#define EMAC_CFG_BR         ((unsigned int) 0x1 <<  2) 					/* (EMAC) Bit rate.                         */
#define EMAC_CFG_CAF        ((unsigned int) 0x1 <<  4) 					/* (EMAC) Copy all frames.                  */
#define EMAC_CFG_NBC        ((unsigned int) 0x1 <<  5) 					/* (EMAC) No broadcast.                     */
#define EMAC_CFG_MTI        ((unsigned int) 0x1 <<  6) 					/* (EMAC) Multicast hash enable             */
#define EMAC_CFG_UNI        ((unsigned int) 0x1 <<  7) 					/* (EMAC) Unicast hash enable.              */
#define EMAC_CFG_BIG        ((unsigned int) 0x1 <<  8) 					/* (EMAC) Receive 1522 bytes.               */
#define EMAC_CFG_EAE        ((unsigned int) 0x1 <<  9) 					/* (EMAC) External address match enable.    */
#define EMAC_CFG_CLK_HCLK_8               ((unsigned int) 0x0 << 10) 	/* (EMAC) HCLK divided by 8                 */
#define EMAC_CFG_CLK_HCLK_16              ((unsigned int) 0x1 << 10) 	/* (EMAC) HCLK divided by 16                */
#define EMAC_CFG_CLK_HCLK_32              ((unsigned int) 0x2 << 10) 	/* (EMAC) HCLK divided by 32                */
#define EMAC_CFG_CLK_HCLK_64              ((unsigned int) 0x3 << 10) 	/* (EMAC) HCLK divided by 64                */
#define EMAC_CFG_RTY        ((unsigned int) 0x1 << 12) 					/* (EMAC)  */
#define EMAC_CFG_RMII       ((unsigned int) 0x1 << 13) 					/* (EMAC)  */
/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */
#define EMAC_SR_MDIO       ((unsigned int) 0x1 <<  1) 					/* (EMAC)  */
#define EMAC_SR_IDLE       ((unsigned int) 0x1 <<  2) 					/* (EMAC)  */
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register --------  */
#define EMAC_TCR_LEN        ((unsigned int) 0x7FF <<  0)   
#define EMAC_TCR_NCRC       ((unsigned int) 0x1 << 15)   
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register --------  */
#define EMAC_TSR_OVR        ((unsigned int) 0x1 <<  0)   
#define EMAC_TSR_COL        ((unsigned int) 0x1 <<  1)   
#define EMAC_TSR_RLE        ((unsigned int) 0x1 <<  2)   
#define EMAC_TSR_TXIDLE     ((unsigned int) 0x1 <<  3)   
#define EMAC_TSR_BNQ        ((unsigned int) 0x1 <<  4)   
#define EMAC_TSR_COMP       ((unsigned int) 0x1 <<  5)   
#define EMAC_TSR_UND        ((unsigned int) 0x1 <<  6)   
/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register --------  */
#define EMAC_RSR_BNA        ((unsigned int) 0x1 <<  0)   
#define EMAC_RSR_REC        ((unsigned int) 0x1 <<  1)  
#define EMAC_RSR_OVR        ((unsigned int) 0x1 <<  2)  
 
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register --------  */
#define EMAC_ISR_DONE       ((unsigned int) 0x1 <<  0)   
#define EMAC_ISR_RCOM       ((unsigned int) 0x1 <<  1)   
#define EMAC_ISR_RBNA       ((unsigned int) 0x1 <<  2)   
#define EMAC_ISR_TOVR       ((unsigned int) 0x1 <<  3)   
#define EMAC_ISR_TUND       ((unsigned int) 0x1 <<  4)   
#define EMAC_ISR_RTRY       ((unsigned int) 0x1 <<  5)   
#define EMAC_ISR_TBRE       ((unsigned int) 0x1 <<  6)   
#define EMAC_ISR_TCOM       ((unsigned int) 0x1 <<  7)   
#define EMAC_ISR_TIDLE      ((unsigned int) 0x1 <<  8)   
#define EMAC_ISR_LINK       ((unsigned int) 0x1 <<  9)   
#define EMAC_ISR_ROVR       ((unsigned int) 0x1 << 10)   
#define EMAC_ISR_HRESP      ((unsigned int) 0x1 << 11)   
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register --------  */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */ 
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register --------    */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register --------   */
#define EMAC_PHY_DATA       ((unsigned int) 0xFFFF <<  0)   
#define EMAC_PHY_CODE       ((unsigned int) 0x3 << 16)  
#define EMAC_PHY_REGA       ((unsigned int) 0x1F << 18)  
#define EMAC_PHY_PHYA       ((unsigned int) 0x1F << 23)
  
#define EMAC_PHY_RW_R       ((unsigned int) 0x2 << 28)  
#define EMAC_PHY_RW_W       ((unsigned int) 0x1 << 28)  

#define EMAC_PHY_HIGH       ((unsigned int) 0x1 << 30)  
#define EMAC_PHY_LOW        ((unsigned int) 0x1 << 31)  

#define EMAC_RECV_DESC_HAVE_DATA (1<<0) 
#define EMAC_RECV_DESC_WRAP		 (1<<1)