📄 at91rm9200.h
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AT91_REG PMC_MCKR; /* Master Clock Register */ AT91_REG Reserved36[3]; /* */ AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */ AT91_REG PMC_IER; /* Interrupt Enable Register */ AT91_REG PMC_IDR; /* Interrupt Disable Register */ AT91_REG PMC_SR; /* Status Register */ AT91_REG PMC_IMR; /* Interrupt Mask Register */}PMC_S;#endif#define RTC_BASE_ADDR 0xFFFFFE00#ifndef _ASMLANGUAGEtypedef struct _RTC_S { AT91_REG RTC_CR; /* Control Register */ AT91_REG RTC_MR; /* Mode Register */ AT91_REG RTC_TIMR; /* Time Register */ AT91_REG RTC_CALR; /* Calendar Register */ AT91_REG RTC_TIMALR; /* Time Alarm Register */ AT91_REG RTC_CALALR; /* Calendar Alarm Register */ AT91_REG RTC_SR; /* Status Register */ AT91_REG RTC_SCCR; /* Status Clear Command Register */ AT91_REG RTC_IER; /* Interrupt Enable Register */ AT91_REG RTC_IDR; /* Interrupt Disable Register */ AT91_REG RTC_IMR; /* Interrupt Mask Register */ AT91_REG RTC_VER; /* Valid Entry Register */} RTC_S;#endif/*----------------------------MC--------------------*/ #define MC_BASE_ADDR 0xFFFFFF00 #define MC_RCR_OFFSET 0 #define MC_ASR_OFFSET 0x4 #define MC_AASR_OFFSET 0x8 #define MC_MPR_OFFSET 0x0c /*-----------------------------SMC--------------------*/#define SMC_BASE_ADDR (EBI_BASE_ADDR+0x10)#define SMC_CSR0_OFFSET 0#define SMC_CSR2_OFFSET 0x08#define SMC_CSR5_OFFSET 0x14 #define SMC_CSR7_OFFSET 0x1C#define SMC_CSR0_NWS (0x0a) /*for 120ns flash, 60M ,wait state should be 10 */#define SMC_CSR0_WSEN (0x01<<7)#define SMC_CSR0_TDF (0x1<<8)#define SMC_CSR0_BAT (0<<12) #define SMC_CSR0_DBW (0x1<<13)#define SMC_CSR0_DRP (0x0<<15)#define SMC_CSR0_ACSS (0x0<<16)#define SMC_CSR0_RWSETUP (0x0<<24)#define SMC_CSR0_RW_HOLD (0x0<<28)#define SMC_CSR2_NWS (0x7F) /*for 120ns flash, 60M ,wait state should be 10 */#define SMC_CSR2_WSEN (0x01<<7)#define SMC_CSR2_TDF (0xF<<8) #define SMC_CSR2_DBW (0x1<<13)#define SMC_CSR5_NWS (0x7f) #define SMC_CSR5_WSEN (0x01<<7)#define SMC_CSR5_TDF (0xf<<8)#define SMC_CSR5_BAT (0x1<<12) #define SMC_CSR5_DBW (0x1<<13)#define SMC_CSR5_DRP (0x0<<15)#define SMC_CSR5_ACSS (0x3<<16)#define SMC_CSR5_RWSETUP (0x7<<24)#define SMC_CSR5_RW_HOLD (0x7<<29)#define SMC_CSR7_NWS (0x2) #define SMC_CSR7_WSEN (0x1<<7)#define SMC_CSR7_TDF (0xf<<8)#define SMC_CSR7_BAT (0x1<<12) #define SMC_CSR7_DBW (0x1<<13)#define SMC_CSR7_DRP (0x0<<15)#define SMC_CSR7_ACSS (0x0<<16)#define SMC_CSR7_RWSETUP (0x7<<24)#define SMC_CSR7_RW_HOLD (0x7<<29)#define SMC_CSR0_VALUE (SMC_CSR0_NWS|SMC_CSR0_WSEN|SMC_CSR0_TDF|SMC_CSR0_BAT|SMC_CSR0_DBW\ |SMC_CSR0_DRP|SMC_CSR0_ACSS|SMC_CSR0_RWSETUP|SMC_CSR0_RW_HOLD) #define SMC_CSR2_VALUE ((SMC_CSR2_NWS & 0x4)|SMC_CSR2_WSEN|(SMC_CSR2_TDF) & 0x100|SMC_CSR2_DBW)#define SMC_CSR5_VALUE (SMC_CSR5_NWS|SMC_CSR5_WSEN|SMC_CSR5_TDF|SMC_CSR5_BAT|SMC_CSR5_DBW\ |SMC_CSR5_DRP|SMC_CSR5_ACSS|SMC_CSR5_RWSETUP|SMC_CSR5_RW_HOLD)#define SPI_BASE_ADDR 0xFFFE0000#ifndef _ASMLANGUAGEtypedef struct _SPI_S { AT91_REG SPI_CR; /* Control Register */ AT91_REG SPI_MR; /* Mode Register */ AT91_REG SPI_RDR; /* Receive Data Register */ AT91_REG SPI_TDR; /* Transmit Data Register */ AT91_REG SPI_SR; /* Status Register */ AT91_REG SPI_IER; /* Interrupt Enable Register */ AT91_REG SPI_IDR; /* Interrupt Disable Register */ AT91_REG SPI_IMR; /* Interrupt Mask Register */ AT91_REG Reserved0[4]; /* */ AT91_REG SPI_CSR[4]; /* Chip Select Register */ AT91_REG Reserved1[48]; /* */ PDC_S SPI_PDC;}SPI_S;#endif#define SSC0_BASE_ADDR 0xFFFD0000#define SSC1_BASE_ADDR 0xFFFD4000#define SSC2_BASE_ADDR 0xFFFD8000#ifndef _ASMLANGUAGEtypedef struct _SSC_S { AT91_REG SSC_CR; /* Control Register */ AT91_REG SSC_CMR; /* Clock Mode Register */ AT91_REG Reserved0[2]; /* */ AT91_REG SSC_RCMR; /* Receive Clock ModeRegister */ AT91_REG SSC_RFMR; /* Receive Frame Mode Register */ AT91_REG SSC_TCMR; /* Transmit Clock Mode Register */ AT91_REG SSC_TFMR; /* Transmit Frame Mode Register */ AT91_REG SSC_RHR; /* Receive Holding Register */ AT91_REG SSC_THR; /* Transmit Holding Register */ AT91_REG Reserved1[2]; /* */ AT91_REG SSC_RSHR; /* Receive Sync Holding Register */ AT91_REG SSC_TSHR; /* Transmit Sync Holding Register */ AT91_REG SSC_RC0R; /* Receive Compare 0 Register */ AT91_REG SSC_RC1R; /* Receive Compare 1 Register */ AT91_REG SSC_SR; /* Status Register */ AT91_REG SSC_IER; /* Interrupt Enable Register */ AT91_REG SSC_IDR; /* Interrupt Disable Register */ AT91_REG SSC_IMR; /* Interrupt Mask Register */ AT91_REG Reserved2[44]; /* */ PDC_S SSC_PDC;}SSC_S;#endif#define TWI_BASE_ADDR 0xFFFB8000#define EEPROM_PAGE_SIZE 32#define EEPROM_MAX_SIZE 8192#define IICCLK 50000#ifndef _ASMLANGUAGEtypedef struct _TWI_S{ AT91_REG TWI_CR; /* Control Register */ AT91_REG TWI_MMR; /* Master Mode Register */ AT91_REG TWI_SMR; /* Slave Mode Register */ AT91_REG TWI_IADR; /* Internal Address Register */ AT91_REG TWI_CWGR; /* Clock Waveform Generator Register */ AT91_REG Reserved0[3]; /* */ AT91_REG TWI_SR; /* Status Register */ AT91_REG TWI_IER; /* Interrupt Enable Register */ AT91_REG TWI_IDR; /* Interrupt Disable Register */ AT91_REG TWI_IMR; /* Interrupt Mask Register */ AT91_REG TWI_RHR; /* Receive Holding Register */ AT91_REG TWI_THR; /* Transmit Holding Register */}TWI_S;#endif/* definitions *//*Reset values for Registers*/#define TWI_CR_START (1<<0)#define TWI_CR_STOP (1<<1)#define TWI_CR_MSEN (1<<2)#define TWI_CR_MSDIS (1<<3)#define TWI_CR_SWRST (1<<7)#define TWI_MMR_ADSIZE_NONE (0<<8)#define TWI_MMR_ADSIZE_8BIT (1<<8)#define TWI_MMR_ADSIZE_16BIT (2<<8)#define TWI_MMR_ADSIZE_24BIT (3<<8)#define TWI_MMR_MREAD (1<<12)#define TWI_MMR_DADR (0x7f<<16)#define TWI_SR_TXCOMP (1<<0)#define TWI_SR_RXRDY (1<<1)#define TWI_SR_TXRDY (1<<2)#define TWI_SR_OVRE (1<<6)#define TWI_SR_UNRE (1<<7)#define TWI_SR_NACK (1<<8)#define TWI_IE_DR_TXCOMP (1<<0)#define TWI_IE_DR_RXRDY (1<<1)#define TWI_IE_DR_TXRDY (1<<2)#define TWI_IE_DR_OVRE (1<<6)#define TWI_IE_DR_UNRE (1<<7)#define TWI_IE_DR_NACK (1<<8)#define UART0_BASE_ADDR 0xFFFC0000#define UART1_BASE_ADDR 0xFFFC4000#define UART2_BASE_ADDR 0xFFFC8000#define UART3_BASE_ADDR 0xFFFCC000#ifndef _ASMLANGUAGE#include "sioLib.h"typedef struct _UART_S{ AT91_REG US_CR; /* Control Register */ AT91_REG US_MR; /* Mode Register */ AT91_REG US_IER; /* Interrupt Enable Register */ AT91_REG US_IDR; /* Interrupt Disable Register */ AT91_REG US_IMR; /* Interrupt Mask Register */ AT91_REG US_CSR; /* Channel Status Register */ AT91_REG US_RHR; /* Receiver Holding Register */ AT91_REG US_THR; /* Transmitter Holding Register */ AT91_REG US_BRGR; /* Baud Rate Generator Register */ AT91_REG US_RTOR; /* Receiver Time-out Register */ AT91_REG US_TTGR; /* Transmitter Time-guard Register */ AT91_REG Reserved0[5]; /* */ AT91_REG US_FIDI; /* FI_DI_Ratio Register */ AT91_REG US_NER; /* Nb Errors Register */ AT91_REG US_XXR; /* XON_XOFF Register */ AT91_REG US_IF; /* IRDA_FILTER Register */ AT91_REG Reserved1[44]; /* */ PDC_S US_PDC;} UART_S;typedef struct _AT91_CHAN{ /* must be first */ SIO_CHAN sio; /* standard SIO_CHAN element */ /* callbacks */ STATUS (*getTxChar) (); STATUS (*putRcvChar) (); void * getTxArg; void * putRcvArg; /* register addresses */ UART_S *regs; /*UART Registers*/ UINT32 level; /* Interrupt Level for this device*/ UINT32 clkdiv; /* misc */ UINT32 options; /* Hardware options */ int intrmode; /* current mode (interrupt or poll) */ int baudRate; /* input clock frequency */ UINT32 errcount; } AT91_CHAN;#endif#define N_AT91_UART_CHANNELS 4/* * for US_CR: */#define UART_CR_RESET_RECV (1<<2)#define UART_CR_RESET_TRAN (1<<3)#define UART_CR_RX_ENA (1<<4)#define UART_CR_RX_DIS (1<<5)#define UART_CR_TX_ENA (1<<6)#define UART_CR_TX_DIS (1<<7)#define UART_CR_RESET_STATUS (1<<8)#define UART_CR_START_BREAK (1<<9)#define UART_CR_STOP_BREAK (1<<10)#define UART_CR_START_TIME_OUT (1<<11)#define UART_CR_SEND_ADDR (1<<12)#define UART_CR_RSTIT (1<<13)#define UART_CR_RESET_NACK (1<<14)#define UART_CR_RESTART_TIMEOUT (1<<15)⌨️ 快捷键说明
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