at91rm9200.h

atmel9200 vxworks bsp

		AT91_REG resv0;
		AT91_REG resv1;
		AT91_REG AIC_IECR;		/*Interrupt Enable Command Register*/ 
		AT91_REG AIC_IDCR;		/*Interrupt Disable Command Register*/
		AT91_REG AIC_ICCR;		/*Interrupt Clear Command Register*/  
		AT91_REG AIC_ISCR;		/*Interrupt Set	Command	Register*/    
		AT91_REG AIC_EOICR;		/*End of Interrupt Command Register*/ 
		AT91_REG AIC_SPU;		/*Spurious Interrupt Vector Register*/
		AT91_REG AIC_DCR;		/*Debug	Control	Register*/	      
		AT91_REG resv2;
		AT91_REG AIC_FFER;		/*Fast Forcing Enable Register*/			
		AT91_REG AIC_FFDR;		/*Fast Forcing Disable Register	AIC_FFDR Write-only */	
		AT91_REG AIC_FFSR;		/*Fast Forcing Status Register AIC_FFSR	Read-only 0x0*/	
	}AIC_S;	
	
#endif
	
	
#define	AIC_SMR_EDGETRIG	(1<<5)
#define AIC_SMR_PRIO_BIT	0

	
#define	INT_LVL_FIQ					PHER_AIC 		/*Advanced Interrupt Controller	FIQ*/
#define	INT_LVL_SYSIRQ				PHER_SYSIRQ 	
#define	INT_LVL_PIOA				PHER_PIOA 		/*Parallel I/O Controller A*/
#define	INT_LVL_PIOB				PHER_PIOB 		/*Parallel I/O Controller B*/
#define	INT_LVL_PIOC				PHER_PIOC 		/*Parallel I/O Controller C*/
#define	INT_LVL_PIOD				PHER_PIOD 		/*Parallel I/O Controller D*/
#define	INT_LVL_UART0				PHER_US0 		/* UART	0 */
#define	INT_LVL_UART1				PHER_US1 		/* UART	1 */
#define	INT_LVL_UART2				PHER_US2 		/* UART	2 */
#define	INT_LVL_UART3				PHER_US3 		/* UART	3 */
#define	INT_LVL_MULT_CARD			PHER_MCI 		/*Multimedia Card Interface*/
#define	INT_LVL_USB_DEV_PORT		PHER_UDP 		/*UDP USB Device Port*/	
#define	INT_LVL_TWO_WIRE_IF			PHER_TWI 		/*Two-wire Interface*/
#define	INT_LVL_SPI					PHER_SPI 		/*Serial Peripheral Interface*/	
#define	INT_LVL_SSC0				PHER_SSC0 		/*Synchronous Serial Controller	0*/
#define	INT_LVL_SSC1				PHER_SSC1 		/*Synchronous Serial Controller	1*/
#define	INT_LVL_SSC2				PHER_SSC2 		/*Synchronous Serial Controller	2*/
#define	INT_LVL_TC0					PHER_TC0 		/*Timer/Counter	0*/
#define	INT_LVL_TC1					PHER_TC1 		/*Timer/Counter	1*/
#define	INT_LVL_TC2					PHER_TC2 		/*Timer/Counter	2*/
#define	INT_LVL_TC3					PHER_TC3 		/*Timer/Counter	3*/
#define	INT_LVL_TC4					PHER_TC4 		/*Timer/Counter	4*/
#define	INT_LVL_TC5					PHER_TC5 		/*Timer/Counter	5*/
#define	INT_LVL_USB_HOST_PORT		PHER_UHP 		/*USB Host Port*/
#define	INT_LVL_EMAC				PHER_EMAC  		/*Ethernet MAC*/
#define	INT_LVL_EXT_IRQ0			PHER_AICIRQ0		
#define	INT_LVL_EXT_IRQ1			PHER_AICIRQ1			
#define	INT_LVL_EXT_IRQ2			PHER_AICIRQ2			
#define	INT_LVL_EXT_IRQ3			PHER_AICIRQ3			
#define	INT_LVL_EXT_IRQ4			PHER_AICIRQ4			
#define	INT_LVL_EXT_IRQ5			PHER_AICIRQ5			
#define	INT_LVL_EXT_IRQ6			PHER_AICIRQ6			
	
	
#define	INT_VEC_FIQ				IVEC_TO_INUM(INT_LVL_FIQ)			
#define	INT_VEC_SYSIRQ			IVEC_TO_INUM(INT_LVL_SYSIRQ)		
	
#define	INT_VEC_PIOA			IVEC_TO_INUM(INT_LVL_PIOA)		
#define	INT_VEC_PIOB			IVEC_TO_INUM(INT_LVL_PIOB)		
#define	INT_VEC_PIOC			IVEC_TO_INUM(INT_LVL_PIOC)		
#define	INT_VEC_PIOD			IVEC_TO_INUM(INT_LVL_PIOD)		
	
#define	INT_VEC_UART0			IVEC_TO_INUM(INT_LVL_UART0)		
#define	INT_VEC_UART1			IVEC_TO_INUM(INT_LVL_UART1)		
#define	INT_VEC_UART2			IVEC_TO_INUM(INT_LVL_UART2)		
#define	INT_VEC_UART3			IVEC_TO_INUM(INT_LVL_UART3)		
	
#define	INT_VEC_MULT_CARD		IVEC_TO_INUM(INT_LVL_MULT_CARD)	      
#define	INT_VEC_USB_DEV_PORT	IVEC_TO_INUM(INT_LVL_USB_DEV_PORT)	      
#define	INT_VEC_TWO_WIRE_IF		IVEC_TO_INUM(INT_LVL_TWO_WIRE_IF)	      
#define	INT_VEC_SPI				IVEC_TO_INUM(INT_LVL_SPI)		      
#define	INT_VEC_SSC0			IVEC_TO_INUM(INT_LVL_SSC0)		      
#define	INT_VEC_SSC1			IVEC_TO_INUM(INT_LVL_SSC1)		      
#define	INT_VEC_SSC2			IVEC_TO_INUM(INT_LVL_SSC2)		      
	
#define	INT_VEC_TC0				IVEC_TO_INUM(INT_LVL_TC0)		      
#define	INT_VEC_TC1				IVEC_TO_INUM(INT_LVL_TC1)		      
#define	INT_VEC_TC2				IVEC_TO_INUM(INT_LVL_TC2)		      
#define	INT_VEC_TC3				IVEC_TO_INUM(INT_LVL_TC3)		      
#define	INT_VEC_TC4				IVEC_TO_INUM(INT_LVL_TC4)		      
#define	INT_VEC_TC5				IVEC_TO_INUM(INT_LVL_TC5)		      
#define	INT_VEC_USB_HOST_PORT	IVEC_TO_INUM(INT_LVL_USB_HOST_PORT)	      
#define	INT_VEC_EMAC			IVEC_TO_INUM(INT_LVL_EMAC)		      
#define	INT_VEC_EXT_IRQ0		IVEC_TO_INUM(INT_LVL_EXT_IRQ0)	      
#define	INT_VEC_EXT_IRQ1		IVEC_TO_INUM(INT_LVL_EXT_IRQ1)	      
#define	INT_VEC_EXT_IRQ2		IVEC_TO_INUM(INT_LVL_EXT_IRQ2)	      
#define	INT_VEC_EXT_IRQ3		IVEC_TO_INUM(INT_LVL_EXT_IRQ3)	      
#define	INT_VEC_EXT_IRQ4		IVEC_TO_INUM(INT_LVL_EXT_IRQ4)	      
#define	INT_VEC_EXT_IRQ5		IVEC_TO_INUM(INT_LVL_EXT_IRQ5)	      
#define	INT_VEC_EXT_IRQ6		IVEC_TO_INUM(INT_LVL_EXT_IRQ6)	

#ifndef _ASMLANGUAGE

typedef struct _EBI_S {
	AT91_REG	 EBI_CSA; 	/* Chip Select Assignment Register*/
	AT91_REG	 EBI_CFGR; 	/* Configuration Register*/
} EBI_S;

#endif

#define	EBI_BASE_ADDR	0xFFFFFF60

#define	EBI_CSA_OFFSET	(0)
#define	EBI_CFGR_OFFSET	(0x04)

#define	EBI_CSA_CS0A	0
#define	EBI_CSA_CS1A	(0x1<<1)
#define	EBI_CSA_CS3A	(0x0<<3)
#define	EBI_CSA_CS4A	(0x0<<4)

#define	EBI_CSA_VALUE	(EBI_CSA_CS0A|EBI_CSA_CS1A|EBI_CSA_CS3A|EBI_CSA_CS4A)

		/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
#define PDC_PTCR_RXTEN       ((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable	  */
#define PDC_PTCR_RXTDIS      ((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable	  */
#define PDC_PTCR_TXTEN       ((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable  */
#define PDC_PTCR_TXTDIS      ((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */

/*---------------------------PIOC-------------------*/
#define PIOA_BASE_ADDR	(0xFFFFF400)
#define PIOB_BASE_ADDR	(0xFFFFF600)
#define	PIOC_BASE_ADDR	(0xFFFFF800)
#define PIOD_BASE_ADDR	(0xFFFFFA00)

#define	PIO_PDR_OFFSET	(0x04)
#define	PIO_ASR_OFFSET	(0x70)
#define	PIO_BSR_OFFSET	(0x74)

#define	PIOC_ENABLE_D16	(0xFFFF0000)

#ifndef _ASMLANGUAGE
typedef struct _AT91_PIO_S
{
	AT91_REG	 PIO_PER; 	/* PIO Enable Register			*/
	AT91_REG	 PIO_PDR; 	/* PIO Disable Register                 */
	AT91_REG	 PIO_PSR; 	/* PIO Status Register                  */
	AT91_REG	 Resv0[1]; 	/*                                      */
	AT91_REG	 PIO_OER; 	/* Output Enable Register               */
	AT91_REG	 PIO_ODR; 	/* Output Disable Registerr             */
	AT91_REG	 PIO_OSR; 	/* Output Status Register               */
	AT91_REG	 Resv1[1]; 	/*                                      */
	AT91_REG	 PIO_IFER; 	/* Input Filter Enable Register         */
	AT91_REG	 PIO_IFDR; 	/* Input Filter Disable Register        */
	AT91_REG	 PIO_IFSR; 	/* Input Filter Status Register         */
	AT91_REG	 Resv2[1]; 	/*                                      */
	AT91_REG	 PIO_SODR; 	/* Set Output Data Register             */
	AT91_REG	 PIO_CODR; 	/* Clear Output Data Register           */
	AT91_REG	 PIO_ODSR; 	/* Output Data Status Register          */
	AT91_REG	 PIO_PDSR; 	/* Pin Data Status Register             */
	AT91_REG	 PIO_IER; 	/* Interrupt Enable Register            */
	AT91_REG	 PIO_IDR; 	/* Interrupt Disable Register           */
	AT91_REG	 PIO_IMR; 	/* Interrupt Mask Register              */
	AT91_REG	 PIO_ISR; 	/* Interrupt Status Register            */
	AT91_REG	 PIO_MDER; 	/* Multi-driver Enable Register         */
	AT91_REG	 PIO_MDDR; 	/* Multi-driver Disable Register        */
	AT91_REG	 PIO_MDSR; 	/* Multi-driver Status Register         */
	AT91_REG	 Resv3[1]; 	/*                                      */
	AT91_REG	 PIO_PPUDR; 	/* Pull-up Disable Register             */
	AT91_REG	 PIO_PPUER; 	/* Pull-up Enable Register              */
	AT91_REG	 PIO_PPUSR; 	/* Pad Pull-up Status Register          */
	AT91_REG	 Resv4[1]; 	/*                                      */
	AT91_REG	 PIO_ASR; 	/* Select A Register                    */
	AT91_REG	 PIO_BSR; 	/* Select B Register                    */
	AT91_REG	 PIO_ABSR; 	/* AB Select Status Register            */
	AT91_REG	 Resv5[9]; 	/*                                      */
	AT91_REG	 PIO_OWER; 	/* Output Write Enable Register         */
	AT91_REG	 PIO_OWDR; 	/* Output Write Disable Register        */
	AT91_REG	 PIO_OWSR; 	/* Output Write Status Register         */
	AT91_REG	 Resv6[85]; 	/*                                      */
}AT91_PIO_S;                             

#endif


#define AT91_PIOA_ASR_VALUE	 0xFFFFFFFF
#define AT91_PIOA_BSR_VALUE	 0x00000000
#define AT91_PIOA_OER_VALUE	 (0&(~(AT91_PIOA_ASR_VALUE|AT91_PIOA_BSR_VALUE)))
#define AT91_PIOA_ODR_VALUE	 ( 0x00000000 )


#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) 
#define AT91C_PA30_DRXD     ((unsigned int) AT91C_PIO_PA30) 
#define AT91C_PA30_CTS2     ((unsigned int) AT91C_PIO_PA30)
#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) 
#define AT91C_PA31_DTXD     ((unsigned int) AT91C_PIO_PA31) 
#define AT91C_PA31_RTS2     ((unsigned int) AT91C_PIO_PA31)


#define AT91_PIOB_ASR_VALUE	 0x3FFC0000
#define AT91_PIOB_BSR_VALUE	 0x0000003F
#define AT91_PIOB_OER_VALUE	(0x0003FC00&(~(AT91_PIOB_ASR_VALUE|AT91_PIOB_BSR_VALUE)))
#define AT91_PIOB_ODR_VALUE	(0x000003c0)
                      
#define AT91_PIOC_ASR_VALUE	 0xFFFF3FCA
#define AT91_PIOC_BSR_VALUE	 0x00000000
#define AT91_PIOC_OER_VALUE	(0x0000c035&(~(AT91_PIOC_ASR_VALUE|AT91_PIOC_BSR_VALUE)))
#define AT91_PIOC_ODR_VALUE	(0x00000000 )


#define AT91_PIOD_ASR_VALUE	 0x00000000
#define AT91_PIOD_BSR_VALUE	 0x00000000
#define AT91_PIOD_OER_VALUE	(0x03FFFFFF&(~(AT91_PIOD_ASR_VALUE|AT91_PIOD_BSR_VALUE)))
#define AT91_PIOD_ODR_VALUE	(0x00000000)

/*---------------------------PMC--------------------------*/     
#define	PMC_BASE_ADDR 0xFFFFFC00  
#define PMC_CKGR_PLLAR_OFFSET	(0x28)
#define PMC_IDR_OFFSET			(0x64)
#define PMC_SR_OFFSET			(0x68)
#define PMC_MCKR_OFFSET			(0x30)
#define PMC_CKGR_MOR_OFFSET		(0x20)


#define PMC_SCER_PCK	(1<<0)
#define PMC_SCER_UDP	(1<<1)
#define PMC_SCER_MCKUDP	(1<<2)
#define PMC_SCER_UHP	(1<<4)

#define PMC_SCER_PCK0	(1<<8)
#define PMC_SCER_PCK1	(1<<9)
#define PMC_SCER_PCK2	(1<<10)
#define PMC_SCER_PCK3	(1<<11)

#define PMC_SCER_STARTUP_VALUE	(PMC_SCER_PCK)
#define PMC_SCDR_STARTUP_VALUE	\
	( PMC_SCER_UDP | PMC_SCER_UHP | PMC_SCER_PCK0 \
		| PMC_SCER_PCK1 | PMC_SCER_PCK2 | PMC_SCER_PCK3 )


#define PMC_PCER_STARTUP_VALUE \
			  ( (1<<PHER_PIOA) | (1<<PHER_PIOB) | (1<<PHER_PIOC) | (1<<PHER_PIOD) \
			  | (1<<PHER_US0) | (1<<PHER_US1) | (1<<PHER_US2) | (1<<PHER_US3) \
			  | (1<<PHER_TWI) | (1<<PHER_SPI) | (1<<PHER_TC0) | (1<<PHER_TC1) \
			  | (1<<PHER_TC2) | (1<<PHER_EMAC) | (1<<PHER_AICIRQ0) | (1<<PHER_AICIRQ1) )

/*
 *	default main osc is disabled, we need to turn on it first
 */
#define PMC_CKGR_MOR_OSCOUNTER	(0xFF)
#define PMC_CKGR_MOR_VALUE 	( (PMC_CKGR_MOR_OSCOUNTER<<8) | 1 )


/*                                                               
    
	  PLLA output frequency = (Mainclock)*(PMC_PLLA_MULA+1)/PMC_PLLA_DIVA
*/
#define	PMC_PLLA_DIVA		(MAIN_CLK_DIV)
#define	PMC_PLLA_PLLACOUNT	((0x3E)<<8) /* delay before PLL	locked */
#define	PMC_PLLA_OUTA		(2<<14)	/* frequency range 150-240M*/
#define	PMC_PLLA_MULA		((MAIN_CLK_MUL-1)<<16) /*	max 2047 ,for 18,432Mhz, output	freq = 179.7M  */
#define	PMC_PLLA_VALUE		((1<<29)|PMC_PLLA_MULA|PMC_PLLA_OUTA|PMC_PLLA_PLLACOUNT|PMC_PLLA_DIVA)	 

#define PMC_SR_MOSCS	   ( 1 )
#define	PMC_SR_LOCKA	   ( 0x1 << 1) /* (PMC)	PLL A Status/Enable/Disable/Mask    */	
#define	PMC_SR_MCKRDY	   ( 0x1 << 3)	/* (PMC) MCK_RDY Status/Enable/Disable/Mask */
#define	DELAY_MAIN_FREQ		1000

#define	PMC_MCKR_CSS	(0x02)	/* use PLLA as source,Fplla as process clock, Fplla/(PMC_MCKR_MDIV+1) as MASTER	clock =	60M */
#define	PMC_MCKR_MDIV	((MASTER_CLK_DIV-1)<<8)
#define	PMC_MCKR_VALUE	(PMC_MCKR_CSS|PMC_MCKR_MDIV)

#ifndef	_ASMLANGUAGE
typedef	struct _PMC_S
{
	AT91_REG	 PMC_SCER; 			/* System Clock Enable Register			*/
	AT91_REG	 PMC_SCDR; 			/* System Clock Disable Register        */
	AT91_REG	 PMC_SCSR; 			/* System Clock Status Register         */
	AT91_REG	 Reserved34[1]; 	/*                                      */
	AT91_REG	 PMC_PCER; 			/* Peripheral Clock Enable Register     */
	AT91_REG	 PMC_PCDR; 			/* Peripheral Clock Disable Register    */
	AT91_REG	 PMC_PCSR; 			/* Peripheral Clock Status Register     */
	AT91_REG	 Reserved35[1]; 	/*                                      */
	AT91_REG	 CKGR_MOR; 			/* Main Oscillator Register             */
	AT91_REG	 CKGR_MCFR; 		/* Main Clock  Frequency Register       */
	AT91_REG	 CKGR_PLLAR; 		/* PLL A Register                       */
	AT91_REG	 CKGR_PLLBR; 		/* PLL B Register                       */