at91rm9200.h

atmel9200 vxworks bsp

/* at91rm9200.h	- ARM Integrator header	file */


#ifndef	INCat91rm9200
#define	INCat91rm9200

#ifdef __cplusplus
extern "C" {
#endif

#ifndef	_ASMLANGUAGE
	typedef volatile unsigned int AT91_REG;
	typedef unsigned char BYTE;
	/*typedef UINT AT91_REG;*/
#endif

#define SLOW_RATE_CLK		32768
#define MAIN_CLK			18432000
#define MAIN_CLK_DIV		(0x04)
#define MAIN_CLK_MUL		(0x27)
#define PROCESS_CLK			(MAIN_CLK*MAIN_CLK_MUL/MAIN_CLK_DIV)
#define MASTER_CLK_DIV		(0x02)
#define MASTER_CLK			(PROCESS_CLK/MASTER_CLK_DIV)
#define MASTER_CLK_UART 87730

		

#define	ARM920T_SSRAM_SIZE 0x4000
#define ARM920T_ROMINIT_C_STACK_TOP 0x3000
#define	ARM920T_INT_ROM_BASE 0x100000
#define	ART920T_INT_ROM_SIZE 0x020000	
	
#define	AT91RM9200_DELAY_VALUE 20

#ifndef _ASMLANGUAGE

typedef struct  _PDC_S
{
	AT91_REG	 PDC_RPR; 			/* Receive Pointer Register                 */
	AT91_REG	 PDC_RCR; 			/* Receive Counter Register                 */
	AT91_REG	 PDC_TPR; 			/* Transmit Pointer Register                */
	AT91_REG	 PDC_TCR; 			/* Transmit Counter Register                */
	AT91_REG	 PDC_RNPR; 			/* Receive Next Pointer Register            */
	AT91_REG	 PDC_RNCR; 			/* Receive Next Counter Register            */
	AT91_REG	 PDC_TNPR; 			/* Transmit Next Pointer Register           */
	AT91_REG	 PDC_TNCR; 			/* Transmit Next Counter Register           */
	AT91_REG	 PDC_PTCR; 			/* PDC Transfer Control Register            */
	AT91_REG	 PDC_PTSR; 			/* PDC Transfer Status Register             */
}PDC_S;
#endif

#define PHER_AIC 		0 		/*Advanced Interrupt Controller FIQ	*/
#define PHER_SYSIRQ     1 
#define PHER_PIOA 		2 		/*Parallel I/O Controller A		*/
#define PHER_PIOB 		3 		/*Parallel I/O Controller B             */
#define PHER_PIOC 		4 		/*Parallel I/O Controller C             */
#define PHER_PIOD 		5 		/*Parallel I/O Controller D             */
#define PHER_US0 		6 		/*USART 0                               */
#define PHER_US1 		7 		/*USART 1                               */
#define PHER_US2 		8 		/*USART 2                               */
#define PHER_US3 		9 		/*USART 3                               */
#define PHER_MCI 		10		/*Multimedia Card Interface             */
#define PHER_UDP 		11		/*USB Device Port                       */
#define PHER_TWI 		12		/*Two-wire Interface                    */
#define PHER_SPI 		13		/*Serial Peripheral Interface           */
#define PHER_SSC0 		14		/*Synchronous Serial Controller 0       */
#define PHER_SSC1 		15		/*Synchronous Serial Controller 1       */
#define PHER_SSC2 		16		/*Synchronous Serial Controller 2       */
#define PHER_TC0 		17		/*Timer/Counter 0                       */
#define PHER_TC1 		18		/*Timer/Counter 1                       */
#define PHER_TC2 		19		/*Timer/Counter 2                       */
#define PHER_TC3 		20		/*Timer/Counter 3                       */
#define PHER_TC4 		21		/*Timer/Counter 4                       */
#define PHER_TC5 		22		/*Timer/Counter 5                       */
#define PHER_UHP 		23		/*USB Host Port                         */
#define PHER_EMAC  		24		/*Ethernet MAC                          */
#define PHER_AICIRQ0 	25		/*Advanced Interrupt Controller IRQ0    */
#define PHER_AICIRQ1 	26		/*Advanced Interrupt Controller IRQ1    */
#define PHER_AICIRQ2 	27		/*Advanced Interrupt Controller IRQ2    */
#define PHER_AICIRQ3 	28		/*Advanced Interrupt Controller IRQ3    */
#define PHER_AICIRQ4 	29		/*Advanced Interrupt Controller IRQ4    */
#define PHER_AICIRQ5 	30		/*Advanced Interrupt Controller IRQ5    */
#define PHER_AICIRQ6   	31

#include "at91timerall.h"	

#define	USB_DEV_BASE_ADDR	0xFFFB0000
#define	MULT_CARD_BASE_ADDR	0xFFFB4000
#define	TWO_WIRE_IF_BASE_ADDR	0xFFFB8000
#define	ETH_MAC_BASE_ADDR		0xFFFBC000
#define	SER_SYNC_CONTROL_BASE_ADDR	0xFFFD0000
#define	SPI_DEV_BASE_ADDR   0xFFFE0000
#define EPSON_S1D13506_BASE_ADDR 0x30000000 /* vga in bank2 */
#define AT91C_BASE_CS5		(0x60000000) /* 10M eth Base Address*/
#define AT91C_BASE_CS7		(0x80000000)
#define LAN91C111_BASE_ADDRESS  0x80000300
#define	BUS		BUS_TYPE_NONE

#ifdef __cplusplus
}
#endif

#endif	/* INCintegratorh */

#define	SDRAMC_BASE_ADDR	(EBI_BASE_ADDR+0x30)


#ifndef _ASMLANGUAGE

typedef struct _SDRAMC_S {
	AT91_REG	 SDRAMC_MR; 	/* SDRAM Controller Mode Register				*/			
	AT91_REG	 SDRAMC_TR; 	/* SDRAM Controller Refresh Timer Register      */
	AT91_REG	 SDRAMC_CR; 	/* SDRAM Controller Configuration Register      */
	AT91_REG	 SDRAMC_SRR; 	/* SDRAM Controller Self Refresh Register       */
	AT91_REG	 SDRAMC_LPR; 	/* SDRAM Controller Low Power Register          */
	AT91_REG	 SDRAMC_IER; 	/* SDRAM Controller Interrupt Enable Register   */
	AT91_REG	 SDRAMC_IDR; 	/* SDRAM Controller Interrupt Disable Register  */
	AT91_REG	 SDRAMC_IMR; 	/* SDRAM Controller Interrupt Mask Register     */
	AT91_REG	 SDRAMC_ISR; 	/* SDRAM Controller Interrupt Mask Register     */
} SDRAMC_S;

#endif	/*_ASMLANGUAGE*/

#define	SDRAMC_MR_OFFSET	(0x0)
#define	SDRAMC_TR_OFFSET	(0x4)
#define	SDRAMC_CR_OFFSET	(0x8)
#define	SDRAMC_SRR_OFFSET	(0xc)
#define	SDRAMC_LPR_OFFSET	(0x10)
#define	SDRAMC_IER_OFFSET	(0x14)
#define	SDRAMC_IDR_OFFSET	(0x18)
#define	SDRAMC_IMR_OFFSET	(0x1c)
#define	SDRAMC_ISR_OFFSET	(0x20)

#define	SDRAMC_CR_NC	(0x1)	/*9bit column*/	
#define	SDRAMC_CR_NR	((0x1)<<2)	/*12bit	row*/
#define	SDRAMC_CR_NB	((0x1)<<4)	/* 4 bank */
#define	SDRAMC_CR_CAS	((0x2)<<5)	/* CAS latency = 2 */
#define	SDRAMC_CR_TWR	((0x2)<<7)	/* write recovery delay	2-15 */	
#define	SDRAMC_CR_TRC	((0x8)<<11)	/* Row Cycle Delay 2-15	*/
#define	SDRAMC_CR_TRP	((0x2)<<15)	/*Row Precharge	Delay*/	
#define	SDRAMC_CR_TRCD	((0x1)<<19)	/*Row to Column	Delay*/	
#define	SDRAMC_CR_TRAS	((0x1)<<23)	/*Active to Precharge Delay*/
#define	SDRAMC_CR_TXSR	((0x1)<<27)	/*Exit Self Refresh to Active Delay*/

#define	SDRAMC_CR_VALUE	0x2188c155

#define	SDRAMC_MR_NORMAL	(0x0)
#define	SDRAMC_MR_NOP		(0x1)
#define	SDRAMC_MR_PRECHG	(0x2)
#define	SDRAMC_MR_LDMODE	(0x3)
#define	SDRAMC_MR_REFLASH	(0x4)
#define	SDRAMC_TR_VALUE		( (MASTER_CLK*13)/1000000 )	/* 12us	for reflash cycle */

#define	DBGU_BASE_ADDR			0xFFFFF200
#ifndef	_ASMLANGUAGE
#include "sioLib.h"
typedef struct	_DBGU_S {                                 
	AT91_REG	 DBGU_CR; 			/* Control Register   					*/
	AT91_REG	 DBGU_MR; 			/* Mode Register                        */
	AT91_REG	 DBGU_IER; 			/* Interrupt Enable Register            */
	AT91_REG	 DBGU_IDR; 			/* Interrupt Disable Register           */
	AT91_REG	 DBGU_IMR; 			/* Interrupt Mask Register              */
	AT91_REG	 DBGU_CSR; 			/* Channel Status Register              */
	AT91_REG	 DBGU_RHR; 			/* Receiver Holding Register            */
	AT91_REG	 DBGU_THR; 			/* Transmitter Holding Register         */
	AT91_REG	 DBGU_BRGR; 		/* Baud Rate Generator Register         */
	AT91_REG	 Reserved3[7]; 		/*                                      */
	AT91_REG	 DBGU_C1R; 			/* Chip ID1 Register                    */
	AT91_REG	 DBGU_C2R; 			/* Chip ID2 Register                    */
	AT91_REG	 DBGU_FNTR; 		/* Force NTRST Register                 */
	AT91_REG	 Reserved4[45]; 	/*                                      */
	PDC_S		 DBGU_PDC;
} DBGU_S;
typedef struct _AT91_DBGU_CHAN
{
    /* must be first */
	
    SIO_CHAN		sio;		/* standard SIO_CHAN element */
	
    /* callbacks */
	
    STATUS	        (*getTxChar) ();
    STATUS	        (*putRcvChar) ();
    void *	        getTxArg;
    void *	        putRcvArg;
	
    /* register addresses */
	
    DBGU_S		*regs;		/*UART Registers*/
	
	
    /* misc */
    UINT32		options;	/* Hardware options */
    int         intrmode;          	/* current mode (interrupt or poll) */
    int         baudRate;       /* input clock frequency */
	UINT32		errcount;
	
} AT91_DBGU_CHAN;


#endif	/* _ASMLANGUANGE */


/*
 *	for DBGU_CR:
 */


#define DBGU_CR_RESET_RECV		(1<<2)
#define DBGU_CR_RESET_TRAN		(1<<3)
#define DBGU_CR_RX_ENA			(1<<4)
#define DBGU_CR_RX_DIS			(1<<5)
#define DBGU_CR_TX_ENA			(1<<6)
#define DBGU_CR_TX_DIS			(1<<7)
#define DBGU_CR_RESET_STATUS	(1<<8)

/*
 *	for DBGU_MR:
 */

#define DBGU_MR_PARITY_EVEN				(0<<9)
#define DBGU_MR_PARITY_ODD				(1<<9)
#define DBGU_MR_PARITY_FORCE_0			(2<<9)
#define DBGU_MR_PARITY_FORCE_1			(3<<9)
#define DBGU_MR_PARITY_NONE				(4<<9)
#define DBGU_MR_TEST_NORMAL_MODE		(0<<14)
#define DBGU_MR_TEST_EACO_MODE			(1<<14)
#define DBGU_MR_TEST_LOCALLOOP_NORMAL	(2<<14)
#define DBGU_MR_TEST_REMOTELOOP_NORMAL	(3<<14)


/*
 *	for DBGU_IER and DBGU_IDR
 */
#define DBGU_IE_DR_RXRDY		(1<<0)		/*RXRDY Interrupt Enable                                  */
#define DBGU_IE_DR_TXRDY        (1<<1)		/*TXRDY Interrupt Enable                                  */
#define DBGU_IE_DR_ENDRX        (1<<3)		/*ENDRX: End of Receive Transfer Interrupt Enable         */
#define DBGU_IE_DR_ENDTX        (1<<4)		/*ENDTX: End of Transmit Interrupt Enable                 */
#define DBGU_IE_DR_OVRE         (1<<5)		/*OVRE: Overrun Error Interrupt Enable                    */
#define DBGU_IE_DR_FRAME        (1<<6)		/*FRAME: Framing Error Interrupt Enable                   */
#define DBGU_IE_DR_PARE         (1<<7)		/*PARE: Parity Error Interrupt Enable                     */
#define DBGU_IE_DR_TXEMPTY      (1<<9)		/*TXEMPTY: TXEMPTY Interrupt Enable                       */
#define DBGU_IE_DR_TXBUFE       (1<<11)		/*TXBUFE: Buffer Empty Interrupt Enable                   */
#define DBGU_IE_DR_RXBUFF       (1<<12)		/*RXBUFF: Buffer Full Interrupt Enable                    */
#define DBGU_IE_DR_COMMTX       (1<<30)		/*Enable COMMTX (from ARM) Interrupt					  */
#define DBGU_IE_DR_COMMRX       (1<<31)		/*Enable COMMRX (from ARM) Interrupt       				  */


#define DBGU_CSR_RXRDY		  (1<<0)		
#define DBGU_CSR_TXRDY        (1<<1)		
#define DBGU_CSR_ENDRX        (1<<3)		
#define DBGU_CSR_ENDTX        (1<<4)		
#define DBGU_CSR_OVRE         (1<<5)		
#define DBGU_CSR_FRAME        (1<<6)		
#define DBGU_CSR_PARE         (1<<7)		
#define DBGU_CSR_TXEMPTY      (1<<9)		
#define DBGU_CSR_TXBUFE       (1<<11)		
#define DBGU_CSR_RXBUFF       (1<<12)		
#define DBGU_CSR_COMMTX       (1<<30)		
#define DBGU_CSR_COMMRX       (1<<31)

#define	AIC_BASE_ADDR	0xFFFFF000
#define	AIC_IDCR_OFFSET	0x124	
#define	AIC_INT_NUM_LEVELS	32	
#define	AT91_SRAM_START_ADDR	0x200000
	
	
#ifndef	_ASMLANGUAGE
	typedef	struct _AIC_S
	{
		AT91_REG AIC_SMR[AIC_INT_NUM_LEVELS];	/*Source Mode Register 0*/  
		AT91_REG AIC_SVR[AIC_INT_NUM_LEVELS];	/*Source Vector	Register 0*/
		AT91_REG AIC_IVR;		/*Interrupt Vector Register*/	  
		AT91_REG AIC_FVR;		/*Fast Interrupt Vector	Register*/
		AT91_REG AIC_ISR;		/*Interrupt Status Register*/	  
		AT91_REG AIC_IPR;		/*Interrupt Pending Register*/	  
		AT91_REG AIC_IMR;		/*Interrupt Mask Register*/	  
		AT91_REG AIC_CISR;		/*Core Interrupt Status	Register*/