rominit_c.c

atmel9200 vxworks bsp

#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "regs.h"
#include "config.h"
#include "arch/arm/mmuArmLib.h"

/*--------------------------------------------------------------------------------------*/
/* Function Name       : AT91F_InitSDRAM						*/
/* Object              : Initialize the SDRAM						*/
/*--------------------------------------------------------------------------------------*/
void InitSDRAMC()
{
	 SDRAMC_S* pSDRAMC = (SDRAMC_S*)SDRAMC_BASE_ADDR;
	 UINT32 *pSDRAM_START = (UINT32*) LOCAL_MEM_LOCAL_ADRS;

	 AT91_PIO_S* pPio = (AT91_PIO_S*) PIOC_BASE_ADDR;

	 pPio->PIO_ASR = PIOC_ENABLE_D16;
	 pPio->PIO_PDR = PIOC_ENABLE_D16; /* Set in Periph mode*/

	 /* MEMC should already Configure
	 *	support all connected memories (CS0 = FLASH; CS1=SDRAM)
	 */

	/*Init SDRAM*/
	pSDRAMC->SDRAMC_CR = SDRAMC_CR_VALUE; /*0x2188c155;*/
	pSDRAMC->SDRAMC_MR = SDRAMC_MR_PRECHG; /*0x02*/;
	*pSDRAM_START = 0;
	pSDRAMC->SDRAMC_MR = SDRAMC_MR_REFLASH/*0x04*/;
	*pSDRAM_START = 0;
	*pSDRAM_START = 0;
	*pSDRAM_START = 0;
	*pSDRAM_START = 0;
	*pSDRAM_START = 0;
	*pSDRAM_START = 0;
	*pSDRAM_START = 0;
	*pSDRAM_START = 0;

	pSDRAMC->SDRAMC_MR = SDRAMC_MR_LDMODE/*0x03*/;
	*(pSDRAM_START + 0x80) = 0;

	pSDRAMC->SDRAMC_TR= SDRAMC_TR_VALUE;/* 0x2e0*/
	*pSDRAM_START = 0;

	pSDRAMC->SDRAMC_MR = SDRAMC_MR_NORMAL/*0*/;
	*pSDRAM_START = 0;
}


/*--------------------------------------------------------------------------------------*/
/* Function Name       : AT91F_SetPLL()							*/
/* Object              : Set the PLLA to 180MHz and Master Clock to 60Mhz		*/
/*--------------------------------------------------------------------------------------*/
void AT91SetupPLL(void)
{
	volatile int tmp = 0;

	/* APMC Initialization for Crystal */
	PMC_S* pPmc = (PMC_S*)PMC_BASE_ADDR;

	pPmc->PMC_IDR = 0xFFFFFFFF;

	/* Setup MEMC to support all connected memories (CS0 = FLASH; CS1=SDRAM) */
	( (EBI_S*)EBI_BASE_ADDR )->EBI_CSA  = EBI_CSA_VALUE;



	/*
	 *	start the main OSC
	 */
	pPmc ->CKGR_MOR = PMC_CKGR_MOR_VALUE;

	/*
	 *	wait main OSC stability
	 */
	tmp = 0;
/*	while(!(pPmc->PMC_SR & PMC_SR_MOSCS ) && (tmp++ < DELAY_MAIN_FREQ)) ;*/

	/* Setup the PLL A */
	pPmc->CKGR_PLLAR = PMC_PLLA_VALUE; /* 0x202cbe03*/

	tmp = 0;
/*	while(!(pPmc->PMC_SR & PMC_SR_LOCKA ) && (tmp++ < DELAY_MAIN_FREQ));*/

	/* Setup the PLL B */
/*	pPmc->CKGR_PLLBR = 0x11973e33; */  /* 48M*/
pPmc->CKGR_PLLBR = 0x10273E05; /* 96M */
	tmp = 0;

	/* com set CS0 cs for flash */
	*((UINT32*)(SMC_BASE_ADDR + SMC_CSR0_OFFSET)) = SMC_CSR0_VALUE;
	/* com set CS2 cs for vga */
#ifdef INCLUDE_WINDML
	*((UINT32*)(SMC_BASE_ADDR + SMC_CSR2_OFFSET)) = SMC_CSR2_VALUE;
#endif /* INCLUDE_WINDML */
/* com set CS5 cs for cs8900 ethanet */
#ifdef INCLUDE_CS8900_END
  *((UINT32*)(SMC_BASE_ADDR + SMC_CSR5_OFFSET)) = SMC_CSR5_VALUE;
#endif
	/* Write in the MCKR dirty value concerning the clock selection CSS then overwrite it in a second sequence */
	pPmc ->PMC_MCKR = 0x203;
	/* Wait until the master clock is established */
	tmp = 0;
/*	while(!(pPmc->PMC_SR & PMC_SR_MCKRDY) && (tmp++ < DELAY_MAIN_FREQ));*/

	/* - Commuting Master Clock from PLLB to PLLA/3 */
	pPmc ->PMC_MCKR = PMC_MCKR_VALUE;
	/* Wait until the master clock is established */
	tmp = 0;
	while(!(pPmc->PMC_SR & PMC_SR_MCKRDY) && (tmp++ < 1000));

}

void DBGU_Printk(
	char *buffer) /* \arg pointer to a string ending by \0 */
{

	DBGU_S* pUSART = (DBGU_S*)DBGU_BASE_ADDR;
	while(*buffer != '\0') {
		while (!(pUSART->DBGU_CSR & DBGU_CSR_TXRDY));
		pUSART->DBGU_THR = *buffer++;
	}
}

/******************added by dongliang***********************/
void AT91SetupDBGU()
{
	AT91_PIO_S* pIOA = (AT91_PIO_S*)PIOA_BASE_ADDR;
	DBGU_S* pUSART = (DBGU_S*)DBGU_BASE_ADDR;
	PDC_S*	pPdc;
	UINT32 baud;


	pIOA -> PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
	pIOA -> PIO_BSR = 0x0;
	pIOA -> PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;

	/******************/
	/* Configure DBGU */
	/******************/

	/* Disable interrupts */
	pUSART->DBGU_IDR = (unsigned int) -1;

	/* Reset receiver and transmitter */
	pUSART->DBGU_CR = DBGU_CR_RESET_RECV | DBGU_CR_RESET_TRAN | DBGU_CR_RX_DIS | DBGU_CR_TX_DIS;

	/* Define the baudrate divisor register */
	baud = 115200;
	pUSART->DBGU_BRGR = ( MASTER_CLK + baud*8 )/(16*baud);

	/*AT91_PDC_Close( &(pUSART->DBGU_PDC) );*/

	pPdc = (PDC_S*) &pUSART->DBGU_PDC;

	pPdc->PDC_PTCR = PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS;
	pPdc->PDC_TNPR = 0;
	pPdc->PDC_TNCR = 0;
	pPdc->PDC_RNPR = 0;
	pPdc->PDC_RNCR = 0;
	pPdc->PDC_TPR = 0;
	pPdc->PDC_TCR = 0;
	pPdc->PDC_TPR = 0;
	pPdc->PDC_TCR = 0;
	pPdc->PDC_PTCR = PDC_PTCR_RXTEN | PDC_PTCR_TXTEN;	/* Enable Rx and Tx */

	/* Define the USART mode */
	pUSART->DBGU_MR = DBGU_MR_TEST_NORMAL_MODE | DBGU_MR_PARITY_NONE;

	/* Enable Transmitter */
	pUSART->DBGU_CR = DBGU_CR_TX_ENA;

}


void romCInitRtn()
{
	AT91SetupPLL();
	InitSDRAMC();
	AT91SetupDBGU();
	DBGU_Printk("");
}