mode0.h

来自「atmel9200 vxworks bsp」· C头文件 代码 · 共 153 行

/*----------------------------------------------------------------------------
/*
/*  File generated by 13506CFG.EXE on Wed Oct 04 00:26:23 2000
/*
/*  Copyright (c) 1998, 2001 Epson Research and Development, Inc.
/*  All rights reserved.
/*
/*----------------------------------------------------------------------------*/

#ifndef __MODE0_H__
#define __MODE0_H__
    {
        {
        0, 240, 320, 16, 59, gpe16Bpp,     /*mode #0: 640 x 480 16Bpp 59Hz */
        0x0101,        /*Version 1.01*/
        480 ,          /*VirtualWidth*/
        1280,          /*VirtualStride*/
        256,           /*PaletteSize*/
        0x30200000L,   /*PhysicalVmemAddr*/
        0x200000L,     /*PhysicalVmemSize*/
        0x30000000L,   /*PhysicalPortAddr*/
        0x200,         /*PhysicalPortSize*/
        0x00000000L,   /*PhysicalBltAddr*/
        0x100000L,     /*PhysicalBltSize*/
        mfLCD,         /*Flags*/
        25175,         /*CLKI*/
        25175,         /*CLKI2*/
        0, 0, 0,       /*LCD Power Control*/
        240, 320, 16, 60,     /* Display2: 640 x 480 16Bpp 60Hz*/
        1280,          /*VirtualStride2*/
        mfLCD,            /*Flags2*/
                       /*DummyBytes[]*/
        },
        {
        /* Panel:  (active)   640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25175kHz)*/ 
        /* CRT:    (inactive) 640x480 60Hz (PCLK=CLKI=25175kHz)*/
        /* Memory: 50ns EDO-DRAM 2-CAS#: 8ms refresh (MCLK=BUSCLK=40000kHz)*/ 

        0x0001,0x00,   /* Miscellaneous Register */
        0x01fc,0x00,   /* Display Mode Register */
        0x0004,0x00,   /* General IO Pins Configuration Register */
        0x0008,0x00,   /* General IO Pins Control Register */
        0x0010,0x11,   /* Memory Clock Configuration Register*/ 
        0x0014,0x32,   /* LCD Pixel Clock Configuration Register*/ 
        0x0018,0x02,   /* CRT/TV Pixel Clock Configuration Register*/ 
        0x001c,0x02,   /* MediaPlug Clock Configuration Register */
        0x001e,0x02,   /* CPU To Memory Wait State Select Register */
        0x0020,0x00,   /* Memory Configuration Register */
        0x0021,0x04,   /* DRAM Refresh Rate Register */
        0x002a,0x12,   /* DRAM Timings Control Register 0 */
        0x002b,0x02,   /* DRAM Timings Control Register 1 */
        0x0030,0x25,   /* Panel Type Register */
        0x0031,0x00,   /* MOD Rate Register */
        0x0032,0x1d,   /* LCD Horizontal Display Width Register */
        0x0034,0x09,   /* LCD Horizontal Non-Display Period Register */
        0x0035,0x01,   /* TFT FPLINE Start Position Register */
        0x0036,0x05,   /* TFT FPLINE Pulse Width Register */
        0x0038,0x3f,   /* LCD Vertical Display Height Register 0 */
        0x0039,0x01,   /* LCD Vertical Display Height Register 1 */
        0x003a,0x16,   /* LCD Vertical Non-Display Period Register */
        0x003b,0x0a,   /* TFT FPFRAME Start Position Register */
        0x003c,0x01,   /* TFT FPFRAME Pulse Width Register */
        0x0040,0x05,   /* LCD Display Mode Register */
        0x0041,0x03,   /* LCD Miscellaneous Register */
        0x0042,0x00,   /* LCD Display Start Address Register 0 */
        0x0043,0x00,   /* LCD Display Start Address Register 1 */
        0x0044,0x00,   /* LCD Display Start Address Register 2 */
        0x0046,0xf0,   /* LCD Memory Address Offset Register 0 */
        0x0047,0x00,   /* LCD Memory Address Offset Register 1 */
        0x0048,0x00,   /* LCD Pixel Panning Register */
        0x004a,0x00,   /* LCD Display FIFO High Threshold Control Register */
        0x004b,0x00,   /* LCD Display FIFO Low Threshold Control Register */
        0x0050,0x4f,   /* CRT/TV Horizontal Display Width Register */
        0x0052,0x13,   /* CRT/TV Horizontal Non-Display Period Register */
        0x0053,0x01,   /* CRT/TV HRTC Start Position Register */
        0x0054,0x0b,   /* CRT/TV HRTC Pulse Width Register */
        0x0056,0xdf,   /* CRT/TV Vertical Display Height Register 0 */
        0x0057,0x01,   /* CRT/TV Vertical Display Height Register 1 */
        0x0058,0x2b,   /* CRT/TV Vertical Non-Display Period Register */
        0x0059,0x09,   /* CRT/TV VRTC Start Position Register */
        0x005a,0x01,   /* CRT/TV VRTC Pulse Width Register */
        0x005b,0x18,   /* TV Output Control Register */
        0x0060,0x03,   /* CRT/TV Display Mode Register */
        0x0062,0x00,   /* CRT/TV Display Start Address Register 0 */
        0x0063,0x00,   /* CRT/TV Display Start Address Register 1 */
        0x0064,0x00,   /* CRT/TV Display Start Address Register 2 */
        0x0066,0x40,   /* CRT/TV Memory Address Offset Register 0 */
        0x0067,0x01,   /* CRT/TV Memory Address Offset Register 1 */
        0x0068,0x00,   /* CRT/TV Pixel Panning Register */
        0x006a,0x00,   /* CRT/TV Display FIFO High Threshold Control Register */
        0x006b,0x00,   /* CRT/TV Display FIFO Low Threshold Control Register */
        0x0070,0x00,   /* LCD Ink/Cursor Control Register */
        0x0071,0x00,   /* LCD Ink/Cursor Start Address Register */
        0x0072,0x00,   /* LCD Cursor X Position Register 0 */
        0x0073,0x00,   /* LCD Cursor X Position Register 1 */
        0x0074,0x00,   /* LCD Cursor Y Position Register 0 */
        0x0075,0x00,   /* LCD Cursor Y Position Register 1 */
        0x0076,0x00,   /* LCD Ink/Cursor Blue Color 0 Register */
        0x0077,0x00,   /* LCD Ink/Cursor Green Color 0 Register */
        0x0078,0x00,   /* LCD Ink/Cursor Red Color 0 Register */
        0x007a,0x00,   /* LCD Ink/Cursor Blue Color 1 Register */
        0x007a,0x00,   /* LCD Ink/Cursor Green Color 1 Register */
        0x007a,0x00,   /* LCD Ink/Cursor Red Color 1 Register */
        0x007e,0x00,   /* LCD Ink/Cursor FIFO Threshold Register */
        0x0080,0x00,   /* CRT/TV Ink/Cursor Control Register */
        0x0081,0x01,   /* CRT/TV Ink/Cursor Start Address Register */
        0x0082,0x00,   /* CRT/TV Cursor X Position Register 0 */
        0x0083,0x00,   /* CRT/TV Cursor X Position Register 1 */
        0x0084,0x00,   /* CRT/TV Cursor Y Position Register 0 */
        0x0085,0x00,   /* CRT/TV Cursor Y Position Register 1 */
        0x0086,0x00,   /* CRT/TV Ink/Cursor Blue Color 0 Register */
        0x0087,0x00,   /* CRT/TV Ink/Cursor Green Color 0 Register */
        0x0088,0x00,   /* CRT/TV Ink/Cursor Red Color 0 Register */
        0x008a,0x1f,   /* CRT/TV Ink/Cursor Blue Color 1 Register */
        0x008b,0x3f,   /* CRT/TV Ink/Cursor Green Color 1 Register */
        0x008c,0x1f,   /* CRT/TV Ink/Cursor Red Color 1 Register */
        0x008e,0x00,   /* CRT/TV Ink/Cursor FIFO Threshold Register */
        0x0100,0x00,   /* BitBlt Control Register 0 */
        0x0101,0x00,   /* BitBlt Control Register 1 */
        0x0102,0x00,   /* BitBlt ROP Code/Color Expansion Register */
        0x0103,0x00,   /* BitBlt Operation Register */
        0x0104,0x00,   /* BitBlt Source Start Address Register 0 */
        0x0105,0x00,   /* BitBlt Source Start Address Register 1 */
        0x0106,0x00,   /* BitBlt Source Start Address Register 2 */
        0x0108,0x00,   /* BitBlt Destination Start Address Register 0 */
        0x0109,0x00,   /* BitBlt Destination Start Address Register 1 */
        0x010a,0x00,   /* BitBlt Destination Start Address Register 2 */
        0x010c,0x00,   /* BitBlt Memory Address Offset Register 0 */
        0x010d,0x00,   /* BitBlt Memory Address Offset Register 1 */
        0x0110,0x00,   /* BitBlt Width Register 0 */
        0x0111,0x00,   /* BitBlt Width Register 1 */
        0x0112,0x00,   /* BitBlt Height Register 0 */
        0x0113,0x00,   /* BitBlt Height Register 1 */
        0x0114,0x00,   /* BitBlt Background Color Register 0 */
        0x0115,0x00,   /* BitBlt Background Color Register 1 */
        0x0118,0x00,   /* BitBlt Foreground Color Register 0 */
        0x0119,0x00,   /* BitBlt Foreground Color Register 1 */
        0x01e0,0x00,   /* Look-Up Table Mode Register */
        0x01e2,0x00,   /* Look-Up Table Address Register */
        0x01e4,0x00,   /* Look-Up Table Data Register */
        0x01f0,0x00,   /* Power Save Configuration Register */
        0x01f1,0x00,   /* Power Save Status Register */
        0x01f4,0x00,   /* CPU-to-Memory Access Watchdog Timer Register */
        0x01fc,0x01,   /* Display Mode Register */
        0xFFFF,0x00 
        }
    },

#undef  Epson16Bpp
#define Epson16Bpp

#endif /* __MODE0_H__ */