events

跨平台性能调试工具

event:0X333 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_LRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU1 marked LRQ flushes
event:0X334 counters:4 um:zero minimum:10000 name:PM_CYC_GRP51 : (Group 51 pm_lsu_mark2) Processor cycles
event:0X335 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP51 : (Group 51 pm_lsu_mark2) Instructions completed
event:0X336 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU0 marked SRQ flushes
event:0X337 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_SRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU1 marked SRQ flushes

#Group 52 pm_lsu_mark3, Load Store Unit Marked Events
event:0X340 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP52 : (Group 52 pm_lsu_mark3) Marked STCX failed
event:0X341 counters:1 um:zero minimum:10000 name:PM_CYC_GRP52 : (Group 52 pm_lsu_mark3) Processor cycles
event:0X342 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_INST_FIN_GRP52 : (Group 52 pm_lsu_mark3) LSU0 finished a marked instruction
event:0X343 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_INST_FIN_GRP52 : (Group 52 pm_lsu_mark3) LSU1 finished a marked instruction
event:0X344 counters:4 um:zero minimum:10000 name:PM_CYC_GRP52 : (Group 52 pm_lsu_mark3) Processor cycles
event:0X345 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP52 : (Group 52 pm_lsu_mark3) Marked group issued
event:0X346 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP52 : (Group 52 pm_lsu_mark3) Marked instruction finished
event:0X347 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP52 : (Group 52 pm_lsu_mark3) Instructions completed

#Group 53 pm_threshold, Group for pipeline threshold studies
event:0X350 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GRP53 : (Group 53 pm_threshold) LMQ LHR merges
event:0X351 counters:1 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP53 : (Group 53 pm_threshold) Threshold timeout
event:0X352 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP53 : (Group 53 pm_threshold) LMQ slot 0 valid
event:0X353 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP53 : (Group 53 pm_threshold) Instructions completed
event:0X354 counters:4 um:zero minimum:10000 name:PM_CYC_GRP53 : (Group 53 pm_threshold) Processor cycles
event:0X355 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP53 : (Group 53 pm_threshold) Marked group issued
event:0X356 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP53 : (Group 53 pm_threshold) Group completed
event:0X357 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP53 : (Group 53 pm_threshold) LMQ slot 0 allocated

#Group 54 pm_pe_bench1, PE Benchmarker group for FP analysis
event:0X360 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP54 : (Group 54 pm_pe_bench1) FPU executed FDIV instruction
event:0X361 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP54 : (Group 54 pm_pe_bench1) FPU executed multiply-add instruction
event:0X362 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP54 : (Group 54 pm_pe_bench1) FXU produced a result
event:0X363 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP54 : (Group 54 pm_pe_bench1) FPU produced a result
event:0X364 counters:4 um:zero minimum:10000 name:PM_CYC_GRP54 : (Group 54 pm_pe_bench1) Processor cycles
event:0X365 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP54 : (Group 54 pm_pe_bench1) FPU executed FSQRT instruction
event:0X366 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP54 : (Group 54 pm_pe_bench1) Instructions completed
event:0X367 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP54 : (Group 54 pm_pe_bench1) FPU executing FMOV or FEST instructions

#Group 55 pm_pe_bench2, PE Benchmarker group for FP stalls analysis
event:0X370 counters:0 um:zero minimum:10000 name:PM_CYC_GRP55 : (Group 55 pm_pe_bench2) Processor cycles
event:0X371 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP55 : (Group 55 pm_pe_bench2) FPU stalled in pipe3
event:0X372 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP55 : (Group 55 pm_pe_bench2) FPU0 produced a result
event:0X373 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP55 : (Group 55 pm_pe_bench2) Instructions completed
event:0X374 counters:4 um:zero minimum:1000 name:PM_FPU_FULL_CYC_GRP55 : (Group 55 pm_pe_bench2) Cycles FPU issue queue full
event:0X375 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP55 : (Group 55 pm_pe_bench2) FPU executed store instruction
event:0X376 counters:6 um:zero minimum:1000 name:PM_FPU1_FIN_GRP55 : (Group 55 pm_pe_bench2) FPU1 produced a result
event:0X377 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP55 : (Group 55 pm_pe_bench2) LSU executed Floating Point load instruction

#Group 56 pm_pe_bench3, PE Benchmarker group for branch analysis
event:0X380 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP56 : (Group 56 pm_pe_bench3) Instructions completed
event:0X381 counters:1 um:zero minimum:1000 name:PM_BIQ_IDU_FULL_CYC_GRP56 : (Group 56 pm_pe_bench3) Cycles BIQ or IDU full
event:0X382 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP56 : (Group 56 pm_pe_bench3) Branches issued
event:0X383 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP56 : (Group 56 pm_pe_bench3) Branch mispredictions due CR bit setting
event:0X384 counters:4 um:zero minimum:1000 name:PM_BRQ_FULL_CYC_GRP56 : (Group 56 pm_pe_bench3) Cycles branch queue full
event:0X385 counters:5 um:zero minimum:10000 name:PM_CYC_GRP56 : (Group 56 pm_pe_bench3) Processor cycles
event:0X386 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP56 : (Group 56 pm_pe_bench3) Branch mispredictions due to target address
event:0X387 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP56 : (Group 56 pm_pe_bench3) Cycles writing to instruction L1

#Group 57 pm_pe_bench4, PE Benchmarker group for L1 and TLB analysis
event:0X390 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP57 : (Group 57 pm_pe_bench4) Data TLB misses
event:0X391 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP57 : (Group 57 pm_pe_bench4) Instruction TLB misses
event:0X392 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache load misses
event:0X393 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache store misses
event:0X394 counters:4 um:zero minimum:10000 name:PM_CYC_GRP57 : (Group 57 pm_pe_bench4) Processor cycles
event:0X395 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP57 : (Group 57 pm_pe_bench4) Instructions completed
event:0X396 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache store references
event:0X397 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache load references

#Group 58 pm_pe_bench5, PE Benchmarker group for L2 analysis
event:0X3A0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP58 : (Group 58 pm_pe_bench5) Instructions completed
event:0X3A1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP58 : (Group 58 pm_pe_bench5) Processor cycles
event:0X3A2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L35_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L3.5
event:0X3A3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2
event:0X3A4 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.5 shared
event:0X3A5 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.75 shared
event:0X3A6 counters:6 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.75 modified
event:0X3A7 counters:7 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.5 modified

#Group 59 pm_pe_bench6, PE Benchmarker group for L3 analysis
event:0X3B0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L3
event:0X3B1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP59 : (Group 59 pm_pe_bench6) Data loaded from memory
event:0X3B2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L35_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L3.5
event:0X3B3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L2
event:0X3B4 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L2.5 shared
event:0X3B5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP59 : (Group 59 pm_pe_bench6) Processor cycles
event:0X3B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP59 : (Group 59 pm_pe_bench6) Instructions completed
event:0X3B7 counters:7 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L2.5 modified

#Group 60 pm_hpmcount1, Hpmcount group for L1 and TLB behavior analysis
event:0X3C0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP60 : (Group 60 pm_hpmcount1) Data TLB misses
event:0X3C1 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP60 : (Group 60 pm_hpmcount1) Cycles LMQ and SRQ empty
event:0X3C2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache load misses
event:0X3C3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache store misses
event:0X3C4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP60 : (Group 60 pm_hpmcount1) Processor cycles
event:0X3C5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP60 : (Group 60 pm_hpmcount1) Instructions completed
event:0X3C6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache store references
event:0X3C7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache load references

#Group 61 pm_hpmcount2, Hpmcount group for computation intensity analysis
event:0X3D0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP61 : (Group 61 pm_hpmcount2) FPU executed FDIV instruction
event:0X3D1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP61 : (Group 61 pm_hpmcount2) FPU executed multiply-add instruction
event:0X3D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP61 : (Group 61 pm_hpmcount2) FPU0 produced a result
event:0X3D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP61 : (Group 61 pm_hpmcount2) FPU1 produced a result
event:0X3D4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP61 : (Group 61 pm_hpmcount2) Processor cycles
event:0X3D5 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP61 : (Group 61 pm_hpmcount2) FPU executed store instruction
event:0X3D6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP61 : (Group 61 pm_hpmcount2) Instructions completed
event:0X3D7 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP61 : (Group 61 pm_hpmcount2) LSU executed Floating Point load instruction

#Group 62 pm_l1andbr, L1 misses and branch misspredict analysis
event:0X3E0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP62 : (Group 62 pm_l1andbr) Instructions completed
event:0X3E1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP62 : (Group 62 pm_l1andbr) Processor cycles
event:0X3E2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP62 : (Group 62 pm_l1andbr) L1 D cache load misses
event:0X3E3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP62 : (Group 62 pm_l1andbr) Branches issued
event:0X3E4 counters:4 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP62 : (Group 62 pm_l1andbr) L1 D cache store misses
event:0X3E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP62 : (Group 62 pm_l1andbr) Processor cycles
event:0X3E6 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP62 : (Group 62 pm_l1andbr) Branch mispredictions due CR bit setting
event:0X3E7 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP62 : (Group 62 pm_l1andbr) Branch mispredictions due to target address

#Group 63 pm_imix, Instruction mix: loads, stores and branches
event:0X3F0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP63 : (Group 63 pm_imix) Instructions completed
event:0X3F1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP63 : (Group 63 pm_imix) Processor cycles
event:0X3F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP63 : (Group 63 pm_imix) L1 D cache load misses
event:0X3F3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP63 : (Group 63 pm_imix) Branches issued
event:0X3F4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP63 : (Group 63 pm_imix) Processor cycles
event:0X3F5 counters:5 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP63 : (Group 63 pm_imix) L1 D cache store misses
event:0X3F6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP63 : (Group 63 pm_imix) L1 D cache store references
event:0X3F7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP63 : (Group 63 pm_imix) L1 D cache load references