events

跨平台性能调试工具

event:0X263 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP38 : (Group 38 pm_lsu_store1) LSU1 L1 D cache store references
event:0X264 counters:4 um:zero minimum:10000 name:PM_CYC_GRP38 : (Group 38 pm_lsu_store1) Processor cycles
event:0X265 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_lsu_store1) Instructions completed
event:0X266 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP38 : (Group 38 pm_lsu_store1) L1 D cache store misses
event:0X267 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP38 : (Group 38 pm_lsu_store1) L1 D cache entries invalidated from L2

#Group 39 pm_lsu_store2, LSU Store Events
event:0X270 counters:0 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP39 : (Group 39 pm_lsu_store2) LSU0 SRQ store forwarded
event:0X271 counters:1 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP39 : (Group 39 pm_lsu_store2) LSU1 SRQ store forwarded
event:0X272 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP39 : (Group 39 pm_lsu_store2) LSU0 L1 D cache store references
event:0X273 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP39 : (Group 39 pm_lsu_store2) LSU1 L1 D cache store references
event:0X274 counters:4 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP39 : (Group 39 pm_lsu_store2) L1 D cache store misses
event:0X275 counters:5 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_lsu_store2) Processor cycles
event:0X276 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_lsu_store2) Instructions completed
event:0X277 counters:7 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_lsu_store2) Processor cycles

#Group 40 pm_lsu7, Information on the Load Store Unit
event:0X280 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP40 : (Group 40 pm_lsu7) LSU0 DERAT misses
event:0X281 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP40 : (Group 40 pm_lsu7) LSU1 DERAT misses
event:0X282 counters:2 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles
event:0X283 counters:3 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles
event:0X284 counters:4 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP40 : (Group 40 pm_lsu7) L1 reload data source valid
event:0X285 counters:5 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles
event:0X286 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP40 : (Group 40 pm_lsu7) Instructions completed
event:0X287 counters:7 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles

#Group 41 pm_dpfetch, Data Prefetch Events
event:0X290 counters:0 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP41 : (Group 41 pm_dpfetch) D cache new prefetch stream allocated
event:0X291 counters:1 um:zero minimum:1000 name:PM_DC_PREF_L2_CLONE_L3_GRP41 : (Group 41 pm_dpfetch) L2 prefetch cloned with L3
event:0X292 counters:2 um:zero minimum:1000 name:PM_L2_PREF_GRP41 : (Group 41 pm_dpfetch) L2 cache prefetches
event:0X293 counters:3 um:zero minimum:1000 name:PM_L1_PREF_GRP41 : (Group 41 pm_dpfetch) L1 cache data prefetches
event:0X294 counters:4 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_dpfetch) Processor cycles
event:0X295 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP41 : (Group 41 pm_dpfetch) Instructions completed
event:0X296 counters:6 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_dpfetch) Processor cycles
event:0X297 counters:7 um:zero minimum:1000 name:PM_DC_PREF_OUT_STREAMS_GRP41 : (Group 41 pm_dpfetch) Out of prefetch streams

#Group 42 pm_misc, Misc Events for testing
event:0X2A0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP42 : (Group 42 pm_misc) Cycles GCT empty
event:0X2A1 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP42 : (Group 42 pm_misc) Cycles LMQ and SRQ empty
event:0X2A2 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP42 : (Group 42 pm_misc) Hypervisor Cycles
event:0X2A3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP42 : (Group 42 pm_misc) Processor cycles
event:0X2A4 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP42 : (Group 42 pm_misc) One or more PPC instruction completed
event:0X2A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP42 : (Group 42 pm_misc) Instructions completed
event:0X2A6 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP42 : (Group 42 pm_misc) Group completed
event:0X2A7 counters:7 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP42 : (Group 42 pm_misc) Time Base bit transition

#Group 43 pm_mark1, Information on marked instructions
event:0X2B0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP43 : (Group 43 pm_mark1) Marked L1 D cache load misses
event:0X2B1 counters:1 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP43 : (Group 43 pm_mark1) Threshold timeout
event:0X2B2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP43 : (Group 43 pm_mark1) Processor cycles
event:0X2B3 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP43 : (Group 43 pm_mark1) Marked group completed
event:0X2B4 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP43 : (Group 43 pm_mark1) Group marked in IDU
event:0X2B5 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP43 : (Group 43 pm_mark1) Marked group issued
event:0X2B6 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP43 : (Group 43 pm_mark1) Marked instruction finished
event:0X2B7 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP43 : (Group 43 pm_mark1) Instructions completed

#Group 44 pm_mark2, Marked Instructions Processing Flow
event:0X2C0 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP44 : (Group 44 pm_mark2) Marked group dispatched
event:0X2C1 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction BRU processing finished
event:0X2C2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP44 : (Group 44 pm_mark2) Processor cycles
event:0X2C3 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction CRU processing finished
event:0X2C4 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP44 : (Group 44 pm_mark2) Group marked in IDU
event:0X2C5 counters:5 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction FXU processing finished
event:0X2C6 counters:6 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction FPU processing finished
event:0X2C7 counters:7 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction LSU processing finished

#Group 45 pm_mark3, Marked Stores Processing Flow
event:0X2D0 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP45 : (Group 45 pm_mark3) Marked store instruction completed
event:0X2D1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP45 : (Group 45 pm_mark3) Processor cycles
event:0X2D2 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP45 : (Group 45 pm_mark3) Marked store completed with intervention
event:0X2D3 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP45 : (Group 45 pm_mark3) Marked group completed
event:0X2D4 counters:4 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP45 : (Group 45 pm_mark3) Marked group completion timeout
event:0X2D5 counters:5 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP45 : (Group 45 pm_mark3) Marked store sent to GPS
event:0X2D6 counters:6 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP45 : (Group 45 pm_mark3) Marked instruction valid in SRQ
event:0X2D7 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_mark3) Instructions completed

#Group 46 pm_mark4, Marked Loads Processing FLow
event:0X2E0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP46 : (Group 46 pm_mark4) Marked L1 D cache load misses
event:0X2E1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_mark4) Processor cycles
event:0X2E2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP46 : (Group 46 pm_mark4) Marked LRQ flushes
event:0X2E3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP46 : (Group 46 pm_mark4) Marked SRQ flushes
event:0X2E4 counters:4 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP46 : (Group 46 pm_mark4) Marked group completion timeout
event:0X2E5 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP46 : (Group 46 pm_mark4) Marked group issued
event:0X2E6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP46 : (Group 46 pm_mark4) Instructions completed
event:0X2E7 counters:7 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP46 : (Group 46 pm_mark4) Marked unaligned load flushes

#Group 47 pm_mark_lsource, Information on marked data source
event:0X2F0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L3
event:0X2F1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from memory
event:0X2F2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L3.5
event:0X2F3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2
event:0X2F4 counters:4 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.5 shared
event:0X2F5 counters:5 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.75 shared
event:0X2F6 counters:6 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.75 modified
event:0X2F7 counters:7 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.5 modified

#Group 48 pm_mark_lsource2, Information on marked data source
event:0X300 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_mark_lsource2) Instructions completed
event:0X301 counters:1 um:zero minimum:10000 name:PM_CYC_GRP48 : (Group 48 pm_mark_lsource2) Processor cycles
event:0X302 counters:2 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP48 : (Group 48 pm_mark_lsource2) Marked L1 reload data source valid
event:0X303 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2
event:0X304 counters:4 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.5 shared
event:0X305 counters:5 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.75 shared
event:0X306 counters:6 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.75 modified
event:0X307 counters:7 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.5 modified

#Group 49 pm_mark_lsource3, Information on marked data source
event:0X310 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L3
event:0X311 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from memory
event:0X312 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L3.5
event:0X313 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L2
event:0X314 counters:4 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_mark_lsource3) Processor cycles
event:0X315 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_mark_lsource3) Instructions completed
event:0X316 counters:6 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L2.75 modified
event:0X317 counters:7 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP49 : (Group 49 pm_mark_lsource3) Marked L1 reload data source valid

#Group 50 pm_lsu_mark1, Load Store Unit Marked Events
event:0X320 counters:0 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP50 : (Group 50 pm_lsu_mark1) Marked L1 D cache store misses
event:0X321 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP50 : (Group 50 pm_lsu_mark1) Marked IMR reloaded
event:0X322 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_ULD_GRP50 : (Group 50 pm_lsu_mark1) LSU0 marked unaligned load flushes
event:0X323 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_ULD_GRP50 : (Group 50 pm_lsu_mark1) LSU1 marked unaligned load flushes
event:0X324 counters:4 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_lsu_mark1) Processor cycles
event:0X325 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_lsu_mark1) Instructions completed
event:0X326 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_UST_GRP50 : (Group 50 pm_lsu_mark1) LSU0 marked unaligned store flushes
event:0X327 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_UST_GRP50 : (Group 50 pm_lsu_mark1) LSU1 marked unaligned store flushes

#Group 51 pm_lsu_mark2, Load Store Unit Marked Events
event:0X330 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU0_GRP51 : (Group 51 pm_lsu_mark2) LSU0 L1 D cache load misses
event:0X331 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU1_GRP51 : (Group 51 pm_lsu_mark2) LSU1 L1 D cache load misses
event:0X332 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_LRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU0 marked LRQ flushes