events

跨平台性能调试工具

event:0X0593 counters:3 um:zero minimum:1000 name:PM_VMX_FLOAT_MULTICYCLE_GRP89 : (Group 89 pm_vmx5) VMX multi-cycle floating point instruction issued

#Group 90 pm_dfu, DFU events
event:0X05A0 counters:0 um:zero minimum:1000 name:PM_DFU_ADD_GRP90 : (Group 90 pm_dfu) DFU add type instruction
event:0X05A1 counters:1 um:zero minimum:1000 name:PM_DFU_ADD_SHIFTED_BOTH_GRP90 : (Group 90 pm_dfu) DFU add type with both operands shifted
event:0X05A2 counters:2 um:zero minimum:1000 name:PM_DFU_BACK2BACK_GRP90 : (Group 90 pm_dfu) DFU back to back operations executed
event:0X05A3 counters:3 um:zero minimum:1000 name:PM_DFU_CONV_GRP90 : (Group 90 pm_dfu) DFU convert from fixed op

#Group 91 pm_dfu2, DFU events
event:0X05B0 counters:0 um:zero minimum:1000 name:PM_DFU_ENC_BCD_DPD_GRP91 : (Group 91 pm_dfu2) DFU Encode BCD to DPD
event:0X05B1 counters:1 um:zero minimum:1000 name:PM_DFU_EXP_EQ_GRP91 : (Group 91 pm_dfu2) DFU operand exponents are equal for add type
event:0X05B2 counters:2 um:zero minimum:1000 name:PM_DFU_FIN_GRP91 : (Group 91 pm_dfu2) DFU instruction finish
event:0X05B3 counters:3 um:zero minimum:1000 name:PM_DFU_SUBNORM_GRP91 : (Group 91 pm_dfu2) DFU result is a subnormal

#Group 92 pm_fab, Fabric events
event:0X05C0 counters:0 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP92 : (Group 92 pm_fab) Fabric command issued
event:0X05C1 counters:1 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP92 : (Group 92 pm_fab) Fabric command retried
event:0X05C2 counters:2 um:zero minimum:1000 name:PM_FAB_DCLAIM_GRP92 : (Group 92 pm_fab) Dclaim operation, locally mastered
event:0X05C3 counters:3 um:zero minimum:1000 name:PM_FAB_DMA_GRP92 : (Group 92 pm_fab) DMA operation, locally mastered

#Group 93 pm_fab2, Fabric events
event:0X05D0 counters:0 um:zero minimum:1000 name:PM_FAB_NODE_PUMP_GRP93 : (Group 93 pm_fab2) Node pump operation, locally mastered
event:0X05D1 counters:1 um:zero minimum:1000 name:PM_FAB_RETRY_NODE_PUMP_GRP93 : (Group 93 pm_fab2) Retry of a node pump, locally mastered
event:0X05D2 counters:2 um:zero minimum:1000 name:PM_FAB_RETRY_SYS_PUMP_GRP93 : (Group 93 pm_fab2) Retry of a system pump, locally mastered  
event:0X05D3 counters:3 um:zero minimum:1000 name:PM_FAB_SYS_PUMP_GRP93 : (Group 93 pm_fab2) System pump operation, locally mastered

#Group 94 pm_fab3, Fabric events
event:0X05E0 counters:0 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP94 : (Group 94 pm_fab3) Fabric command issued
event:0X05E1 counters:1 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP94 : (Group 94 pm_fab3) Fabric command retried
event:0X05E2 counters:2 um:zero minimum:1000 name:PM_FAB_ADDR_COLLISION_GRP94 : (Group 94 pm_fab3) local node launch collision with off-node address   
event:0X05E3 counters:3 um:zero minimum:1000 name:PM_FAB_MMIO_GRP94 : (Group 94 pm_fab3) MMIO operation, locally mastered

#Group 95 pm_mem_dblpump, Double pump
event:0X05F0 counters:0 um:zero minimum:1000 name:PM_MEM_DP_RQ_GLOB_LOC_GRP95 : (Group 95 pm_mem_dblpump) Memory read queue marking cache line double pump state from global to local
event:0X05F1 counters:1 um:zero minimum:1000 name:PM_MEM_DP_RQ_LOC_GLOB_GRP95 : (Group 95 pm_mem_dblpump) Memory read queue marking cache line double pump state from local to global
event:0X05F2 counters:2 um:zero minimum:1000 name:PM_MEM_DP_CL_WR_GLOB_GRP95 : (Group 95 pm_mem_dblpump) cache line write setting double pump state to global
event:0X05F3 counters:3 um:zero minimum:1000 name:PM_MEM_DP_CL_WR_LOC_GRP95 : (Group 95 pm_mem_dblpump) cache line write setting double pump state to local

#Group 96 pm_mem0_dblpump, MCS0 Double pump
event:0X0600 counters:0 um:zero minimum:1000 name:PM_MEM0_DP_RQ_GLOB_LOC_GRP96 : (Group 96 pm_mem0_dblpump) Memory read queue marking cache line double pump state from global to local side 0
event:0X0601 counters:1 um:zero minimum:1000 name:PM_MEM0_DP_RQ_LOC_GLOB_GRP96 : (Group 96 pm_mem0_dblpump) Memory read queue marking cache line double pump state from local to global side 0
event:0X0602 counters:2 um:zero minimum:1000 name:PM_MEM0_DP_CL_WR_GLOB_GRP96 : (Group 96 pm_mem0_dblpump) cacheline write setting dp to global side 0
event:0X0603 counters:3 um:zero minimum:1000 name:PM_MEM0_DP_CL_WR_LOC_GRP96 : (Group 96 pm_mem0_dblpump) cacheline write setting dp to local side 0

#Group 97 pm_mem1_dblpump, MCS1 Double pump
event:0X0610 counters:0 um:zero minimum:1000 name:PM_MEM1_DP_RQ_GLOB_LOC_GRP97 : (Group 97 pm_mem1_dblpump) Memory read queue marking cache line double pump state from global to local side 1
event:0X0611 counters:1 um:zero minimum:1000 name:PM_MEM1_DP_RQ_LOC_GLOB_GRP97 : (Group 97 pm_mem1_dblpump) Memory read queue marking cache line double pump state from local to global side 1
event:0X0612 counters:2 um:zero minimum:1000 name:PM_MEM1_DP_CL_WR_GLOB_GRP97 : (Group 97 pm_mem1_dblpump) cacheline write setting dp to global side 1
event:0X0613 counters:3 um:zero minimum:1000 name:PM_MEM1_DP_CL_WR_LOC_GRP97 : (Group 97 pm_mem1_dblpump) cacheline write setting dp to local side 1

#Group 98 pm_gxo, GX outbound
event:0X0620 counters:0 um:zero minimum:1000 name:PM_GXO_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Outbound GX bus utilizations (# of cycles in use)
event:0X0621 counters:1 um:zero minimum:1000 name:PM_GXO_ADDR_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Outbound GX address utilization (# of cycles address out is valid)
event:0X0622 counters:2 um:zero minimum:1000 name:PM_GXO_DATA_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Outbound GX Data utilization (# of cycles data out is valid)
event:0X0623 counters:3 um:zero minimum:1000 name:PM_GXI_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Inbound GX bus utilizations (# of cycles in use)

#Group 99 pm_gxi, GX inbound
event:0X0630 counters:0 um:zero minimum:1000 name:PM_GXI_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Inbound GX bus utilizations (# of cycles in use)
event:0X0631 counters:1 um:zero minimum:1000 name:PM_GXI_ADDR_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Inbound GX address utilization (# of cycle address is in valid)
event:0X0632 counters:2 um:zero minimum:1000 name:PM_GXI_DATA_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Inbound GX Data utilization (# of cycle data in is valid)
event:0X0633 counters:3 um:zero minimum:1000 name:PM_GXO_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Outbound GX bus utilizations (# of cycles in use)

#Group 100 pm_gx_dma, DMA events
event:0X0640 counters:0 um:zero minimum:1000 name:PM_GXO_CYC_BUSY_GRP100 : (Group 100 pm_gx_dma) Outbound GX bus utilizations (# of cycles in use)
event:0X0641 counters:1 um:zero minimum:1000 name:PM_GXI_CYC_BUSY_GRP100 : (Group 100 pm_gx_dma) Inbound GX bus utilizations (# of cycles in use)
event:0X0642 counters:2 um:zero minimum:1000 name:PM_GX_DMA_READ_GRP100 : (Group 100 pm_gx_dma) DMA Read Request
event:0X0643 counters:3 um:zero minimum:1000 name:PM_GX_DMA_WRITE_GRP100 : (Group 100 pm_gx_dma) All DMA Write Requests (including dma wrt lgcy)

#Group 101 pm_L1_misc, L1 misc events
event:0X0650 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP101 : (Group 101 pm_L1_misc) Instruction fetched from L1
event:0X0651 counters:1 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP101 : (Group 101 pm_L1_misc) Cycles writing to instruction L1
event:0X0652 counters:2 um:zero minimum:1000 name:PM_NO_ITAG_CYC_GRP101 : (Group 101 pm_L1_misc) Cyles no ITAG available
event:0X0653 counters:3 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP101 : (Group 101 pm_L1_misc) IMC matched instructions completed

#Group 102 pm_L2_data, L2 load and store data
event:0X0660 counters:0 um:zero minimum:1000 name:PM_L2_LD_REQ_DATA_GRP102 : (Group 102 pm_L2_data) L2 data load requests
event:0X0661 counters:1 um:zero minimum:1000 name:PM_L2_LD_MISS_DATA_GRP102 : (Group 102 pm_L2_data) L2 data load misses
event:0X0662 counters:2 um:zero minimum:1000 name:PM_L2_ST_REQ_DATA_GRP102 : (Group 102 pm_L2_data) L2 data store requests
event:0X0663 counters:3 um:zero minimum:1000 name:PM_L2_ST_MISS_DATA_GRP102 : (Group 102 pm_L2_data) L2 data store misses

#Group 103 pm_L2_ld_inst, L2 Load instructions
event:0X0670 counters:0 um:zero minimum:1000 name:PM_L2_LD_REQ_INST_GRP103 : (Group 103 pm_L2_ld_inst) L2 instruction load requests
event:0X0671 counters:1 um:zero minimum:1000 name:PM_L2_LD_MISS_INST_GRP103 : (Group 103 pm_L2_ld_inst) L2 instruction load misses
event:0X0672 counters:2 um:zero minimum:1000 name:PM_L2_MISS_GRP103 : (Group 103 pm_L2_ld_inst) L2 cache misses
event:0X0673 counters:3 um:zero minimum:1000 name:PM_L2_PREF_LD_GRP103 : (Group 103 pm_L2_ld_inst) L2 cache prefetches

#Group 104 pm_L2_castout_invalidate, L2 castout and invalidate events
event:0X0680 counters:0 um:zero minimum:1000 name:PM_L2_CASTOUT_MOD_GRP104 : (Group 104 pm_L2_castout_invalidate) L2 castouts - Modified (M, Mu, Me)
event:0X0681 counters:1 um:zero minimum:1000 name:PM_L2_CASTOUT_SHR_GRP104 : (Group 104 pm_L2_castout_invalidate) L2 castouts - Shared (T, Te, Si, S)
event:0X0682 counters:2 um:zero minimum:1000 name:PM_IC_INV_L2_GRP104 : (Group 104 pm_L2_castout_invalidate) L1 I cache entries invalidated from L2
event:0X0683 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP104 : (Group 104 pm_L2_castout_invalidate) L1 D cache entries invalidated from L2

#Group 105 pm_L2_ldst_reqhit, L2 load and store requests and hits
event:0X0690 counters:0 um:zero minimum:1000 name:PM_LD_REQ_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 load requests 
event:0X0691 counters:1 um:zero minimum:1000 name:PM_LD_HIT_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 D cache load hits
event:0X0692 counters:2 um:zero minimum:1000 name:PM_ST_REQ_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 store requests
event:0X0693 counters:3 um:zero minimum:1000 name:PM_ST_HIT_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 D cache store hits

#Group 106 pm_L2_ld_data_slice, L2 data loads by slice
event:0X06A0 counters:0 um:zero minimum:1000 name:PM_L2SA_LD_REQ_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice A data load requests
event:0X06A1 counters:1 um:zero minimum:1000 name:PM_L2SA_LD_MISS_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice A data load misses
event:0X06A2 counters:2 um:zero minimum:1000 name:PM_L2SB_LD_REQ_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice B data load requests
event:0X06A3 counters:3 um:zero minimum:1000 name:PM_L2SB_LD_MISS_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice B data load misses

#Group 107 pm_L2_ld_inst_slice, L2 instruction loads by slice
event:0X06B0 counters:0 um:zero minimum:1000 name:PM_L2SA_LD_REQ_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice A instruction load requests
event:0X06B1 counters:1 um:zero minimum:1000 name:PM_L2SA_LD_MISS_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice A instruction load misses
event:0X06B2 counters:2 um:zero minimum:1000 name:PM_L2SB_LD_REQ_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice B instruction load requests
event:0X06B3 counters:3 um:zero minimum:1000 name:PM_L2SB_LD_MISS_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice B instruction load misses

#Group 108 pm_L2_st_slice, L2 slice stores by slice
event:0X06C0 counters:0 um:zero minimum:1000 name:PM_L2SA_ST_REQ_GRP108 : (Group 108 pm_L2_st_slice) L2 slice A store requests
event:0X06C1 counters:1 um:zero minimum:1000 name:PM_L2SA_ST_MISS_GRP108 : (Group 108 pm_L2_st_slice) L2 slice A store misses
event:0X06C2 counters:2 um:zero minimum:1000 name:PM_L2SB_ST_REQ_GRP108 : (Group 108 pm_L2_st_slice) L2 slice B store requests
event:0X06C3 counters:3 um:zero minimum:1000 name:PM_L2SB_ST_MISS_GRP108 : (Group 108 pm_L2_st_slice) L2 slice B store misses

#Group 109 pm_L2miss_slice, L2 misses by slice
event:0X06D0 counters:0 um:zero minimum:1000 name:PM_L2SA_MISS_GRP109 : (Group 109 pm_L2miss_slice) L2 slice A misses
event:0X06D1 counters:1 um:zero minimum:1000 name:PM_L2_MISS_GRP109 : (Group 109 pm_L2miss_slice) L2 cache misses
event:0X06D2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP109 : (Group 109 pm_L2miss_slice) Data loaded missed L2
event:0X06D3 counters:3 um:zero minimum:1000 name:PM_L2SB_MISS_GRP109 : (Group 109 pm_L2miss_slice) L2 slice B misses

#Group 110 pm_L2_castout_slice, L2 castouts by slice
event:0X06E0 counters:0 um:zero minimum:1000 name:PM_L2SA_CASTOUT_MOD_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice A castouts - Modified
event:0X06E1 counters:1 um:zero minimum:1000 name:PM_L2SA_CASTOUT_SHR_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice A castouts - Shared
event:0X06E2 counters:2 um:zero minimum:1000 name:PM_L2SB_CASTOUT_MOD_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice B castouts - Modified
event:0X06E3 counters:3 um:zero minimum:1000 name:PM_L2SB_CASTOUT_SHR_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice B castouts - Shared

#Group 111 pm_L2_invalidate_slice, L2 invalidate by slice
event:0X06F0 counters:0 um:zero minimum:1000 name:PM_L2SA_IC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice A I cache invalidate
event:0X06F1 counters:1 um:zero minimum:1000 name:PM_L2SA_DC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice A D cache invalidate
event:0X06F2 counters:2 um:zero minimum:1000 name:PM_L2SB_IC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice B I cache invalidate
event:0X06F3 counters:3 um:zero minimum:1000 name:PM_L2SB_DC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice B D cache invalidate

#Group 112 pm_L2_ld_reqhit_slice, L2 load requests and hist by slice
event:0X0700 counters:0 um:zero minimum:1000 name:PM_L2SA_LD_REQ_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice A load requests 
event:0X0701 counters:1 um:zero minimum:1000 name:PM_L2SA_LD_HIT_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice A load hits
event:0X0702 counters:2 um:zero minimum:1000 name:PM_L2SB_LD_REQ_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice B load requests 
event:0X0703 counters:3 um:zero minimum:1000 name:PM_L2SB_LD_HIT_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice B