events

跨平台性能调试工具

event:0X02B1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_THRD_PRIO_GRP43 : (Group 43 pm_disp_held7) DISP unit held due to lower priority thread
event:0X02B2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_SPR_GRP43 : (Group 43 pm_disp_held7) DISP unit held due to MTSPR/MFSPR
event:0X02B3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_CR_LOGICAL_GRP43 : (Group 43 pm_disp_held7) DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR

#Group 44 pm_disp_held8, Dispatch held conditions
event:0X02C0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_ISYNC_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to ISYNC 
event:0X02C1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_STCX_CR_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to STCX updating CR 
event:0X02C2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_RU_WQ_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to RU FXU write queue full
event:0X02C3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_FPU_CR_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to FPU updating CR

#Group 45 pm_disp_held9, Dispatch held conditions
event:0X02D0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_ISYNC_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to ISYNC 
event:0X02D1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_FPU_CR_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to FPU updating CR
event:0X02D2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_MULT_GPR_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to multiple/divide multiply/divide GPR dependencies
event:0X02D3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_COMPLETION_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to completion holding dispatch 

#Group 46 pm_sync, Sync events
event:0X02E0 counters:0 um:zero minimum:1000 name:PM_LWSYNC_GRP46 : (Group 46 pm_sync) Isync instruction completed
event:0X02E1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_sync) Processor cycles
event:0X02E2 counters:2 um:zero minimum:1000 name:PM_SYNC_CYC_GRP46 : (Group 46 pm_sync) Sync duration
event:0X02E3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_LSU_SOPS_GRP46 : (Group 46 pm_sync) DISP unit held due to LSU slow ops (sync, tlbie, stcx)

#Group 47 pm_L1_ref, L1 references
event:0X02F0 counters:0 um:zero minimum:1000 name:PM_LD_REF_L1_BOTH_GRP47 : (Group 47 pm_L1_ref) Both units L1 D cache load reference
event:0X02F1 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_GRP47 : (Group 47 pm_L1_ref) L1 D cache load references
event:0X02F2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP47 : (Group 47 pm_L1_ref) L1 D cache store references
event:0X02F3 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_BOTH_GRP47 : (Group 47 pm_L1_ref) Both units L1 D cache store reference

#Group 48 pm_L1_ldst, L1 load/store ref/miss
event:0X0300 counters:0 um:zero minimum:1000 name:PM_ST_REF_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache store references
event:0X0301 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache load references
event:0X0302 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache store misses
event:0X0303 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache load misses

#Group 49 pm_streams, Streams
event:0X0310 counters:0 um:zero minimum:1000 name:PM_DC_PREF_OUT_OF_STREAMS_GRP49 : (Group 49 pm_streams) D cache out of streams
event:0X0311 counters:1 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP49 : (Group 49 pm_streams) D cache new prefetch stream allocated
event:0X0312 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP49 : (Group 49 pm_streams) L1 cache data prefetches
event:0X0313 counters:3 um:zero minimum:1000 name:PM_IBUF_FULL_CYC_GRP49 : (Group 49 pm_streams) Cycles instruction buffer full

#Group 50 pm_flush, Flushes
event:0X0320 counters:0 um:zero minimum:1000 name:PM_FLUSH_GRP50 : (Group 50 pm_flush) Flushes
event:0X0321 counters:1 um:zero minimum:1000 name:PM_FLUSH_ASYNC_GRP50 : (Group 50 pm_flush) Flush caused by asynchronous exception
event:0X0322 counters:2 um:zero minimum:1000 name:PM_FLUSH_FPU_GRP50 : (Group 50 pm_flush) Flush caused by FPU exception
event:0X0323 counters:3 um:zero minimum:1000 name:PM_FLUSH_FXU_GRP50 : (Group 50 pm_flush) Flush caused by FXU exception

#Group 51 pm_prefetch, I cache Prefetches
event:0X0330 counters:0 um:zero minimum:1000 name:PM_IC_REQ_GRP51 : (Group 51 pm_prefetch) I cache demand of prefetch request
event:0X0331 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP51 : (Group 51 pm_prefetch) Instruction prefetch requests
event:0X0332 counters:2 um:zero minimum:1000 name:PM_IC_RELOAD_SHR_GRP51 : (Group 51 pm_prefetch) I cache line reloading to be shared by threads
event:0X0333 counters:3 um:zero minimum:1000 name:PM_IC_PREF_WRITE_GRP51 : (Group 51 pm_prefetch) Instruction prefetch written into I cache

#Group 52 pm_stcx, STCX
event:0X0340 counters:0 um:zero minimum:1000 name:PM_STCX_GRP52 : (Group 52 pm_stcx) STCX executed
event:0X0341 counters:1 um:zero minimum:1000 name:PM_STCX_CANCEL_GRP52 : (Group 52 pm_stcx) stcx cancel by core
event:0X0342 counters:2 um:zero minimum:1000 name:PM_STCX_FAIL_GRP52 : (Group 52 pm_stcx) STCX failed
event:0X0343 counters:3 um:zero minimum:1000 name:PM_LARX_GRP52 : (Group 52 pm_stcx) Larx executed

#Group 53 pm_larx, LARX
event:0X0350 counters:0 um:zero minimum:1000 name:PM_LARX_GRP53 : (Group 53 pm_larx) Larx executed
event:0X0351 counters:1 um:zero minimum:1000 name:PM_LARX_L1HIT_GRP53 : (Group 53 pm_larx) larx hits in L1
event:0X0352 counters:2 um:zero minimum:1000 name:PM_STCX_GRP53 : (Group 53 pm_larx) STCX executed
event:0X0353 counters:3 um:zero minimum:1000 name:PM_STCX_FAIL_GRP53 : (Group 53 pm_larx) STCX failed

#Group 54 pm_thread_cyc, Thread cycles
event:0X0360 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP54 : (Group 54 pm_thread_cyc) One of the threads in run cycles
event:0X0361 counters:1 um:zero minimum:1000 name:PM_THRD_GRP_CMPL_BOTH_CYC_GRP54 : (Group 54 pm_thread_cyc) Cycles group completed by both threads
event:0X0362 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP54 : (Group 54 pm_thread_cyc) Concurrent run instructions
event:0X0363 counters:3 um:zero minimum:1000 name:PM_THRD_BOTH_RUN_CYC_GRP54 : (Group 54 pm_thread_cyc) Both threads in run cycles

#Group 55 pm_misc, Misc
event:0X0370 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP55 : (Group 55 pm_misc) One or more PPC instruction completed
event:0X0371 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP55 : (Group 55 pm_misc) Hypervisor Cycles
event:0X0372 counters:2 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP55 : (Group 55 pm_misc) Threshold timeout
event:0X0373 counters:3 um:zero minimum:1000 name:PM_THRD_LLA_BOTH_CYC_GRP55 : (Group 55 pm_misc) Both threads in Load Look Ahead

#Group 56 pm_misc2, Misc
event:0X0380 counters:0 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP56 : (Group 56 pm_misc2) Cycles MSR(EE) bit off and external interrupt pending
event:0X0381 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP56 : (Group 56 pm_misc2) External interrupts
event:0X0382 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP56 : (Group 56 pm_misc2) Time Base bit transition
event:0X0383 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP56 : (Group 56 pm_misc2) No instructions fetched

#Group 57 pm_misc3, Misc
event:0X0390 counters:0 um:zero minimum:1000 name:PM_ST_FIN_GRP57 : (Group 57 pm_misc3) Store instructions finished
event:0X0391 counters:1 um:zero minimum:1000 name:PM_THRD_L2MISS_GRP57 : (Group 57 pm_misc3) Thread in L2 miss
event:0X0392 counters:2 um:zero minimum:10000 name:PM_CYC_GRP57 : (Group 57 pm_misc3) Processor cycles
event:0X0393 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP57 : (Group 57 pm_misc3) Instructions completed

#Group 58 pm_tlb_slb, TLB and SLB events
event:0X03A0 counters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP58 : (Group 58 pm_tlb_slb) Instruction SLB misses
event:0X03A1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP58 : (Group 58 pm_tlb_slb) Data SLB misses
event:0X03A2 counters:2 um:zero minimum:1000 name:PM_TLB_REF_GRP58 : (Group 58 pm_tlb_slb) TLB reference
event:0X03A3 counters:3 um:zero minimum:1000 name:PM_ITLB_REF_GRP58 : (Group 58 pm_tlb_slb) Instruction TLB reference

#Group 59 pm_slb_miss, SLB Misses
event:0X03B0 counters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP59 : (Group 59 pm_slb_miss) Instruction SLB misses
event:0X03B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP59 : (Group 59 pm_slb_miss) Data SLB misses
event:0X03B2 counters:2 um:zero minimum:1000 name:PM_IERAT_MISS_GRP59 : (Group 59 pm_slb_miss) IERAT miss count
event:0X03B3 counters:3 um:zero minimum:1000 name:PM_SLB_MISS_GRP59 : (Group 59 pm_slb_miss) SLB misses

#Group 60 pm_rejects, Reject events
event:0X03C0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_L2_CORR_GRP60 : (Group 60 pm_rejects) LSU reject due to L2 correctable error
event:0X03C1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_DERAT_MPRED_GRP60 : (Group 60 pm_rejects) LSU reject due to mispredicted DERAT
event:0X03C2 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_FAST_GRP60 : (Group 60 pm_rejects) LSU fast reject
event:0X03C3 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_GRP60 : (Group 60 pm_rejects) LSU reject

#Group 61 pm_rejects2, Reject events
event:0X03D0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_GRP61 : (Group 61 pm_rejects2) Load hit store reject
event:0X03D1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_BOTH_GRP61 : (Group 61 pm_rejects2) Load hit store reject both units
event:0X03D2 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_EXTERN_GRP61 : (Group 61 pm_rejects2) LSU external reject request 
event:0X03D3 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_STEAL_GRP61 : (Group 61 pm_rejects2) LSU reject due to steal

#Group 62 pm_rejects3, Reject events
event:0X03E0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_STQ_FULL_GRP62 : (Group 62 pm_rejects3) LSU reject due to store queue full
event:0X03E1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_SLOW_GRP62 : (Group 62 pm_rejects3) LSU slow reject
event:0X03E2 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_NO_SCRATCH_GRP62 : (Group 62 pm_rejects3) LSU reject due to scratch register not available
event:0X03E3 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_PARTIAL_SECTOR_GRP62 : (Group 62 pm_rejects3) LSU reject due to partial sector valid

#Group 63 pm_rejects4, Unaligned store rejects
event:0X03F0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_UST_BOTH_GRP63 : (Group 63 pm_rejects4) Unaligned store reject both units
event:0X03F1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_UST_GRP63 : (Group 63 pm_rejects4) Unaligned store reject
event:0X03F2 counters:2 um:zero minimum:1000 name:PM_LSU0_REJECT_UST_GRP63 : (Group 63 pm_rejects4) LSU0 unaligned store reject
event:0X03F3 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_UST_GRP63 : (Group 63 pm_rejects4) LSU1 unaligned store reject

#Group 64 pm_rejects5, Unaligned load rejects
event:0X0400 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_ULD_GRP64 : (Group 64 pm_rejects5) Unaligned load reject
event:0X0401 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_ULD_BOTH_GRP64 : (Group 64 pm_rejects5) Unaligned load reject both units
event:0X0402 counters:2 um:zero minimum:1000 name:PM_LSU0_REJECT_ULD_GRP64 : (Group 64 pm_rejects5) LSU0 unaligned load reject
event:0X0403 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_ULD_GRP64 : (Group 64 pm_rejects5) LSU1 unaligned load reject

#Group 65 pm_rejects6, Set mispredictions rejects
event:0X0410 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_SET_MPRED_GRP65 : (Group 65 pm_rejects6) LSU0 reject due to mispredicted set
event:0X0411 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_SET_MPRED_GRP65 : (Group 65 pm_rejects6) LSU1 reject due to mispredicted set
event:0X0412 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_SET_MPRED_GRP65 : (Group 65 pm_rejects6) LSU reject due to mispredicted set
event:0X0413 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP65 : (Group 65 pm_rejects6) Cycles SRQ empty

#Group 66 pm_rejects_unit, Unaligned reject events by unit
event:0X0420 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_ULD_GRP66 : (Group 66 pm_rejects_unit) LSU0 unaligned load reject
event:0X0421 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_UST_GRP66 : (Group 66 pm_rejects_unit) LSU1 unaligned store reject