events

跨平台性能调试工具

event:0X254 counters:4 um:zero minimum:10000 name:PM_CYC_GRP37 : (Group 37 pm_lsu_mark1) Processor cycles
event:0X255 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP37 : (Group 37 pm_lsu_mark1) Instructions completed
event:0X256 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU0 marked unaligned load flushes
event:0X257 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU1 marked unaligned load flushes

#Group 38 pm_lsu_mark2, Load Store Unit Marked Events
event:0X260 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU0_GRP38 : (Group 38 pm_lsu_mark2) LSU0 L1 D cache load misses
event:0X261 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU1_GRP38 : (Group 38 pm_lsu_mark2) LSU1 L1 D cache load misses
event:0X262 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked LRQ flushes
event:0X263 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked LRQ flushes
event:0X264 counters:4 um:zero minimum:10000 name:PM_CYC_GRP38 : (Group 38 pm_lsu_mark2) Processor cycles
event:0X265 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_lsu_mark2) Instructions completed
event:0X266 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked SRQ flushes
event:0X267 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked SRQ flushes

#Group 39 pm_fxu1, Fixed Point events by unit
event:0X270 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
event:0X271 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
event:0X272 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP39 : (Group 39 pm_fxu1) FXU produced a result
event:0X273 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP39 : (Group 39 pm_fxu1) FXU1 busy FXU0 idle
event:0X274 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP39 : (Group 39 pm_fxu1) FXU idle
event:0X275 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP39 : (Group 39 pm_fxu1) FXU busy
event:0X276 counters:6 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP39 : (Group 39 pm_fxu1) FXU0 busy FXU1 idle
event:0X277 counters:7 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_fxu1) Processor cycles

#Group 40 pm_fxu2, Fixed Point events by unit
event:0X280 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP40 : (Group 40 pm_fxu2) Instructions completed
event:0X281 counters:1 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_fxu2) Processor cycles
event:0X282 counters:2 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU1/LS1 queue full
event:0X283 counters:3 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU0/LS0 queue full
event:0X284 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP40 : (Group 40 pm_fxu2) FXU idle
event:0X285 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP40 : (Group 40 pm_fxu2) FXU busy
event:0X286 counters:6 um:zero minimum:1000 name:PM_FXU0_FIN_GRP40 : (Group 40 pm_fxu2) FXU0 produced a result
event:0X287 counters:7 um:zero minimum:1000 name:PM_FXU1_FIN_GRP40 : (Group 40 pm_fxu2) FXU1 produced a result

#Group 41 pm_ifu, pm_ifu
event:0X290 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP41 : (Group 41 pm_ifu) Instruction fetched from L1
event:0X291 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP41 : (Group 41 pm_ifu) Instruction fetched from memory
event:0X292 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP41 : (Group 41 pm_ifu) Instructions fetched from prefetch
event:0X293 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP41 : (Group 41 pm_ifu) No instructions fetched
event:0X294 counters:4 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP41 : (Group 41 pm_ifu) Cycles at least 1 instruction fetched
event:0X295 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP41 : (Group 41 pm_ifu) Instruction fetched from L2.5 modified
event:0X296 counters:6 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_ifu) Processor cycles
event:0X297 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP41 : (Group 41 pm_ifu) Instructions completed

#Group 42 pm_cpi_stack1, CPI stack analysis
event:0X2A0 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU0 busy
event:0X2A1 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU1 busy
event:0X2A2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP42 : (Group 42 pm_cpi_stack1) Flush initiated by LSU
event:0X2A3 counters:3 um:zero minimum:1000 name:PM_FLUSH_LSU_BR_MPRED_GRP42 : (Group 42 pm_cpi_stack1) Flush caused by LSU or branch mispredict
event:0X2A4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by LSU instruction
event:0X2A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP42 : (Group 42 pm_cpi_stack1) Instructions completed
event:0X2A6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by ERAT miss
event:0X2A7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP42 : (Group 42 pm_cpi_stack1) Processor cycles

#Group 43 pm_cpi_stack2, CPI stack analysis
event:0X2B0 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_OTHER_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by other reason
event:0X2B1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP43 : (Group 43 pm_cpi_stack2) Instructions completed
event:0X2B2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load misses
event:0X2B3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP43 : (Group 43 pm_cpi_stack2) Processor cycles
event:0X2B4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by D cache miss
event:0X2B5 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP43 : (Group 43 pm_cpi_stack2) DERAT misses
event:0X2B6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by reject
event:0X2B7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load references

#Group 44 pm_cpi_stack3, CPI stack analysis
event:0X2C0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP44 : (Group 44 pm_cpi_stack3) Instructions completed
event:0X2C1 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_SRQ_FULL_GRP44 : (Group 44 pm_cpi_stack3) GCT empty caused by SRQ full
event:0X2C2 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FXU produced a result
event:0X2C3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FPU produced a result
event:0X2C4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by FXU instruction
event:0X2C5 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP44 : (Group 44 pm_cpi_stack3) FXU busy
event:0X2C6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by DIV instruction
event:0X2C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP44 : (Group 44 pm_cpi_stack3) Processor cycles

#Group 45 pm_cpi_stack4, CPI stack analysis
event:0X2D0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FDIV instruction
event:0X2D1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP45 : (Group 45 pm_cpi_stack4) FPU executed multiply-add instruction
event:0X2D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_cpi_stack4) Instructions completed
event:0X2D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_cpi_stack4) Instructions completed
event:0X2D4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FDIV or FQRT instruction
event:0X2D5 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
event:0X2D6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FPU instruction
event:0X2D7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP45 : (Group 45 pm_cpi_stack4) Processor cycles

#Group 46 pm_cpi_stack5, CPI stack analysis
event:0X2E0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles GCT empty
event:0X2E1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP46 : (Group 46 pm_cpi_stack5) Instructions completed
event:0X2E2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) Flush caused by branch mispredict
event:0X2E3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP46 : (Group 46 pm_cpi_stack5) Branch mispredictions due to target address
event:0X2E4 counters:4 um:zero minimum:1000 name:PM_GCT_EMPTY_IC_MISS_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to I cache miss
event:0X2E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_cpi_stack5) Processor cycles
event:0X2E6 counters:6 um:zero minimum:1000 name:PM_GCT_EMPTY_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to branch mispredict
event:0X2E7 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles writing to instruction L1

#Group 47 pm_data2, data source and LMQ
event:0X2F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 shared
event:0X2F1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
event:0X2F2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 modified
event:0X2F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
event:0X2F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
event:0X2F5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
event:0X2F6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP47 : (Group 47 pm_data2) LMQ slot 0 allocated
event:0X2F7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP47 : (Group 47 pm_data2) LMQ slot 0 valid

#Group 48 pm_fetch_branch, Instruction fetch and branch events
event:0X300 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from L2
event:0X301 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP48 : (Group 48 pm_fetch_branch) Instruction fetched from memory
event:0X302 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from prefetch
event:0X303 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP48 : (Group 48 pm_fetch_branch) Branches issued
event:0X304 counters:4 um:zero minimum:10000 name:PM_CYC_GRP48 : (Group 48 pm_fetch_branch) Processor cycles
event:0X305 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_fetch_branch) Instructions completed
event:0X306 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to CR bit setting
event:0X307 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to target address

#Group 49 pm_l1l2_miss, L1 and L2 miss events
event:0X310 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from L2
event:0X311 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_l1l2_miss) Instructions completed
event:0X312 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from memory
event:0X313 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP49 : (Group 49 pm_l1l2_miss) LSU0 L1 D cache load misses
event:0X314 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP49 : (Group 49 pm_l1l2_miss) One or more PPC instruction completed
event:0X315 counters:5 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_l1l2_miss) Processor cycles
event:0X316 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP49 : (Group 49 pm_l1l2_miss) LSU1 L1 D cache load misses
event:0X317 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP49 : (Group 49 pm_l1l2_miss) L1 D cache load references